Lines Matching +full:0 +full:xc300
28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
49 i-cache-size = <0x8000>; // L1, 32K
50 timebase-frequency = <0>;
51 bus-frequency = <0>;
52 clock-frequency = <0>;
59 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
66 reg = <0 0xef005000 0 0x1000>;
70 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
71 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
72 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
73 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */
74 4 0 0 0xe9000000 0x100000>; /* CS4: USB */
76 nor-boot@0,0 {
79 reg = <0 0 0x8000000>; /* 128MB */
82 partition@0 {
84 reg = <0x00000000 0x6f00000>; /* 111 MB */
88 reg = <0x6f00000 0x1000000>; /* 16 MB */
92 reg = <0x7f00000 0x40000>; /* 256 KB */
96 reg = <0x7f40000 0x40000>; /* 256 KB */
100 reg = <0x7f80000 0x80000>; /* 512 KB */
105 nor-alternate@1,0 {
108 //reg = <0xf0000000 0x08000000>; /* 128MB */
109 reg = <1 0 0x8000000>; /* 128MB */
112 partition@0 {
114 reg = <0x00000000 0x6f00000>; /* 111 MB */
118 reg = <0x6f00000 0x1000000>; /* 16 MB */
122 reg = <0x7f00000 0x40000>; /* 256 KB */
126 reg = <0x7f40000 0x40000>; /* 256 KB */
130 reg = <0x7f80000 0x80000>; /* 512 KB */
135 nand@2,0 {
146 reg = <2 0 0x40000>;
148 partition@0 {
150 reg = <0 0x40000000>;
154 usb@4,0 {
156 reg = <4 0 0x100000>;
168 ranges = <0x0 0 0xef000000 0x100000>;
169 bus-frequency = <0>; // Filled out by uboot.
171 ecm-law@0 {
173 reg = <0x0 0x1000>;
179 reg = <0x1000 0x1000>;
186 reg = <0x2000 0x1000>;
193 reg = <0x6000 0x1000>;
200 reg = <0x20000 0x1000>;
202 cache-size = <0x100000>; // L2, 1M
209 #size-cells = <0>;
210 cell-index = <0>;
212 reg = <0x3000 0x100>;
219 reg = <0x48>;
224 reg = <0x4c>;
229 reg = <0x51>;
234 reg = <0x54>;
240 reg = <0x68>;
245 reg = <0x6a>;
251 reg = <0x18>;
254 polarity = <0x00>;
260 reg = <0x1c>;
263 polarity = <0x00>;
269 reg = <0x1d>;
272 polarity = <0x00>;
275 /* CompactPCI signals (sysen, GA[4:0]) */
278 reg = <0x1e>;
281 polarity = <0x00>;
287 reg = <0x1f>;
290 polarity = <0x00>;
296 #size-cells = <0>;
299 reg = <0x3100 0x100>;
309 reg = <0xc300 0x4>;
310 ranges = <0x0 0xc100 0x200>;
312 dma-channel@0 {
315 reg = <0x0 0x80>;
316 cell-index = <0>;
323 reg = <0x80 0x80>;
331 reg = <0x100 0x80>;
339 reg = <0x180 0x80>;
350 reg = <0x21300 0x4>;
351 ranges = <0x0 0x21100 0x200>;
352 cell-index = <0>;
353 dma-channel@0 {
356 reg = <0x0 0x80>;
357 cell-index = <0>;
364 reg = <0x80 0x80>;
372 reg = <0x100 0x80>;
380 reg = <0x180 0x80>;
387 /* eTSEC 1 front panel 0 */
391 cell-index = <0>;
395 reg = <0x24000 0x1000>;
396 ranges = <0x0 0x24000 0x1000>;
406 #size-cells = <0>;
408 reg = <0x520 0x20>;
413 reg = <0x1>;
418 reg = <0x2>;
423 reg = <0x3>;
428 reg = <0x4>;
431 reg = <0x11>;
445 reg = <0x25000 0x1000>;
446 ranges = <0x0 0x25000 0x1000>;
456 #size-cells = <0>;
458 reg = <0x520 0x20>;
461 reg = <0x11>;
467 /* eTSEC 3 PICMG2.16 backplane port 0 */
475 reg = <0x26000 0x1000>;
476 ranges = <0x0 0x26000 0x1000>;
486 #size-cells = <0>;
488 reg = <0x520 0x20>;
491 reg = <0x11>;
505 reg = <0x27000 0x1000>;
506 ranges = <0x0 0x27000 0x1000>;
516 #size-cells = <0>;
518 reg = <0x520 0x20>;
521 reg = <0x11>;
529 cell-index = <0>;
532 reg = <0x4500 0x100>;
533 clock-frequency = <0>;
543 reg = <0x4600 0x100>;
544 clock-frequency = <0>;
551 reg = <0xe0000 0x1000>;
557 reg = <0x41600 0x80>;
558 msi-available-ranges = <0 0x100>;
560 0xe0 0
561 0xe1 0
562 0xe2 0
563 0xe3 0
564 0xe4 0
565 0xe5 0
566 0xe6 0
567 0xe7 0>;
572 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
573 "fsl,sec2.1", "fsl,sec2.0";
574 reg = <0x30000 0x10000>;
579 fsl,exec-units-mask = <0x9fe>;
580 fsl,descriptor-types-mask = <0x3ab0ebf>;
585 #address-cells = <0>;
587 reg = <0x40000 0x40000>;
594 reg = <0xf000 0x1000>;
629 reg = <0x10000 0x5000>;
636 reg = <0x2f000 0x1000>;
643 reg = <0x15000 0x1000>;
664 reg = <0 0xef00a000 0 0x1000>;
665 bus-range = <0 255>;
666 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
667 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
671 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
673 /* IDSEL 0x0 */
674 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
675 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
676 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
677 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
679 pcie@0 {
680 reg = <0x0 0x0 0x0 0x0 0x0>;
684 ranges = <0x2000000 0x0 0x80000000
685 0x2000000 0x0 0x80000000
686 0x0 0x40000000
688 0x1000000 0x0 0x0
689 0x1000000 0x0 0x0
690 0x0 0x100000>;