Lines Matching +full:syscon +full:- +full:pcie +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
41 gpio-controller@18 {
45 #gpio-cells = <2>;
46 gpio-controller;
51 power-control@2a {
66 temperature-sensor@4c {
69 interrupt-parent = <&gpio>;
70 interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */
71 <13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */
72 #address-cells = <1>;
73 #size-cells = <0>;
81 /* Remote temperature sensor (D+/D- connected to P2020 CPU Temperature Diode) */
94 /* MCP79402-I/ST Protected EEPROM */
99 /* ATSHA204-TH-DA-T crypto module */
106 clock-generator@69 {
111 /* MCP79402-I/ST RTC */
115 interrupt-parent = <&gpio>;
116 interrupts = <14 0>; /* GPIO14 - MFP pin */
124 gpio: gpio-controller@fc00 {
125 #interrupt-cells = <2>;
126 interrupt-controller;
129 /* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */
136 /* Connected to port 6 of QCA8337N-AL3C switch */
137 phy-connection-type = "rgmii-id";
139 fixed-link {
141 full-duplex;
147 phy: ethernet-phy@7 {
152 /* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */
159 #address-cells = <1>;
160 #size-cells = <0>;
166 phy-mode = "rgmii-id";
168 fixed-link {
170 full-duplex;
203 phy-mode = "rgmii-id";
205 fixed-link {
207 full-duplex;
215 fsl,tclk-period = <5>;
216 fsl,tmr-prsc = <200>;
217 fsl,tmr-add = <0xcccccccd>;
218 fsl,tmr-fiper1 = <0x3b9ac9fb>;
219 fsl,tmr-fiper2 = <0x0001869b>;
220 fsl,max-adj = <249999999>;
224 /* Connected to port 0 of QCA8337N-AL3C switch */
225 phy-connection-type = "rgmii-id";
227 fixed-link {
229 full-duplex;
240 phy-handle = <&phy>;
241 phy-connection-type = "rgmii-id";
249 bus-width = <4>;
250 cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
263 compatible = "cfi-flash";
265 bank-width = <2>;
266 device-width = <1>;
269 compatible = "fixed-partitions";
270 #address-cells = <1>;
271 #size-cells = <1>;
303 /* free unused space 0x00f00000-0x00f20000 */
306 /* 128 kB for U-Boot Environment Variables */
308 label = "u-boot-env";
312 /* 768 kB for U-Boot Bootloader Image */
314 label = "u-boot";
321 compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
323 nand-ecc-mode = "soft";
324 nand-ecc-algo = "bch";
327 compatible = "fixed-partitions";
328 #address-cells = <1>;
329 #size-cells = <1>;
339 /* LCMXO1200C-3FTN256C FPGA */
343 * is extended version of P1021RDB-PC CPLD v4.1 firmware.
347 * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v
349 compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
351 #address-cells = <1>;
352 #size-cells = <1>;
376 * These bugs have to be workarounded in U-Boot
377 * bootloader. So use system reset via syscon as
378 * a last resort because older U-Boot versions
381 * Reset method via rstcr's global-utilities
384 * syscon-reboot priority level is 192.
386 * So define syscon-reboot with custom priority
390 * than system reset via syscon.
392 compatible = "syscon-reboot";
400 led-controller@13 {
407 compatible = "cznic,turris1x-leds";
409 #address-cells = <1>;
410 #size-cells = <0>;
412 multi-led@0 {
418 multi-led@1 {
422 function-enumerator = <5>;
425 multi-led@2 {
429 function-enumerator = <4>;
432 multi-led@3 {
436 function-enumerator = <3>;
439 multi-led@4 {
443 function-enumerator = <2>;
446 multi-led@5 {
450 function-enumerator = <1>;
453 multi-led@6 {
459 multi-led@7 {
468 pci2: pcie@ffe08000 {
470 * PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller.
472 * Turris 1.0 boards have nothing connected to this PCIe bus,
473 * so system would see only PCIe Root Port of this PCIe Root
479 * P2020 PCIe Root Port does not use PCIe MEM and xHCI controller
480 * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
481 * So allocate 128kB of PCIe MEM for this PCIe bus.
487 pcie@0 {
492 pci1: pcie@ffe09000 {
493 /* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
498 pcie@0 {
503 pci0: pcie@ffe0a000 {
505 * PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card.
508 * additional SIM card slot, both for USB-based WWAN cards.
514 pcie@0 {
520 /include/ "fsl/p2020si-post.dtsi"