Lines Matching +full:0 +full:x00000
31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
65 reg = <0x1000 0x1000>;
72 reg = <0x2000 0x1000>;
79 reg = <0x20000 0x1000>;
81 cache-size = <0x80000>; // L2, 512K
88 #size-cells = <0>;
89 cell-index = <0>;
91 reg = <0x3000 0x100>;
98 reg = <0x48>;
103 reg = <0x68>;
109 #size-cells = <0>;
112 reg = <0x3100 0x100>;
122 reg = <0x21300 0x4>;
123 ranges = <0x0 0x21100 0x200>;
124 cell-index = <0>;
125 dma-channel@0 {
128 reg = <0x0 0x80>;
129 cell-index = <0>;
136 reg = <0x80 0x80>;
144 reg = <0x100 0x80>;
152 reg = <0x180 0x80>;
162 cell-index = <0>;
166 reg = <0x24000 0x1000>;
167 ranges = <0x0 0x24000 0x1000>;
176 #size-cells = <0>;
178 reg = <0x520 0x20>;
180 phy1: ethernet-phy@0 {
206 reg = <0x11>;
219 reg = <0x25000 0x1000>;
220 ranges = <0x0 0x25000 0x1000>;
229 #size-cells = <0>;
231 reg = <0x520 0x20>;
234 reg = <0x11>;
247 reg = <0x26000 0x1000>;
248 ranges = <0x0 0x26000 0x1000>;
257 #size-cells = <0>;
259 reg = <0x520 0x20>;
262 reg = <0x11>;
275 reg = <0x27000 0x1000>;
276 ranges = <0x0 0x27000 0x1000>;
285 #size-cells = <0>;
287 reg = <0x520 0x20>;
290 reg = <0x11>;
297 cell-index = <0>;
300 reg = <0x4500 0x100>; // reg base, size
301 clock-frequency = <0>; // should we fill in in uboot?
311 reg = <0x4600 0x100>; // reg base, size
312 clock-frequency = <0>; // should we fill in in uboot?
320 reg = <0xe0000 0x1000>;
326 #address-cells = <0>;
328 reg = <0x40000 0x40000>;
339 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
344 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
345 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
346 2 0x0 0xe3000000 0x00008000 // CAN (2 x CC770)
347 3 0x0 0xe3010000 0x00008000 // NAND FLASH
351 flash@1,0 {
355 reg = <1 0x0 0x8000000>;
359 partition@0 {
361 reg = <0x00000000 0x00200000>;
365 reg = <0x00200000 0x00300000>;
369 reg = <0x00500000 0x07a00000>;
373 reg = <0x07f00000 0x00040000>;
377 reg = <0x07f40000 0x00040000>;
381 reg = <0x07f80000 0x00080000>;
387 can@2,0 {
389 reg = <2 0x0 0x100>;
401 reg = <2 0x100 0x100>;
411 upm@3,0 {
412 #address-cells = <0>;
413 #size-cells = <0>;
415 reg = <3 0x0 0x800>;
416 fsl,upm-addr-offset = <0x10>;
417 fsl,upm-cmd-offset = <0x08>;
419 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
420 fsl,upm-wait-flags = <0x5>;
423 nand@0 {
427 partition@0 {
429 reg = <0x00000000 0x10000000>;
441 reg = <0xe0008000 0x1000>;
443 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
446 0xe000 0 0 1 &mpic 2 1
447 0xe000 0 0 2 &mpic 3 1
448 0xe000 0 0 3 &mpic 6 1
449 0xe000 0 0 4 &mpic 5 1
452 0x5800 0 0 1 &mpic 6 1
453 0x5800 0 0 2 &mpic 5 1
458 bus-range = <0 0>;
459 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
460 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
464 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
466 /* IDSEL 0x0 (PEX) */
467 0x00000 0 0 1 &mpic 0 1
468 0x00000 0 0 2 &mpic 1 1
469 0x00000 0 0 3 &mpic 2 1
470 0x00000 0 0 4 &mpic 3 1>;
474 bus-range = <0 0xff>;
475 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
476 0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
481 reg = <0xe000a000 0x1000>;
484 pcie@0 {
485 reg = <0 0 0 0 0>;
489 ranges = <0x02000000 0 0xc0000000 0x02000000 0
490 0xc0000000 0 0x20000000
491 0x01000000 0 0x00000000 0x01000000 0
492 0x00000000 0 0x08000000>;