Lines Matching +full:0 +full:x01400000
18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
63 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
67 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
75 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
79 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
87 dcr-reg = <0x0f0 0x009>;
88 #address-cells = <0>;
89 #size-cells = <0>;
91 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
97 dcr-reg = <0x00e 0x002>;
102 dcr-reg = <0x00c 0x002>;
110 clock-frequency = <0>; /* Filled in by U-Boot */
114 dcr-reg = <0x010 0x002>;
119 dcr-reg = <0x180 0x62>;
125 interrupts = < /*TXEOB*/ 0x6 0x4
126 /*RXEOB*/ 0x7 0x4
127 /*SERR*/ 0x1 0x4
128 /*TXDE*/ 0x2 0x4
129 /*RXDE*/ 0x3 0x4
130 /*COAL TX0*/ 0x18 0x2
131 /*COAL TX1*/ 0x19 0x2
132 /*COAL TX2*/ 0x1a 0x2
133 /*COAL TX3*/ 0x1b 0x2
134 /*COAL RX0*/ 0x1c 0x2
135 /*COAL RX1*/ 0x1d 0x2
136 /*COAL RX2*/ 0x1e 0x2
137 /*COAL RX3*/ 0x1f 0x2>;
144 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
145 clock-frequency = <0>; /* Filled in by U-Boot */
149 dcr-reg = <0x012 0x002>;
152 clock-frequency = <0>; /* Filled in by U-Boot */
154 interrupts = <0x6 0x4>;
157 nor_flash@0,0 {
160 reg = <0x0000000 0x00000000 0x04000000>;
163 partition@0 {
165 reg = <0x00000000 0x001e0000>;
169 reg = <0x001e0000 0x00020000>;
173 reg = <0x00200000 0x01400000>;
177 reg = <0x01600000 0x00400000>;
181 reg = <0x01a00000 0x02560000>;
185 reg = <0x03f60000 0x00040000>;
189 reg = <0x03fa0000 0x00060000>;
197 reg = <0xef600200 0x00000008>;
198 virtual-reg = <0xef600200>;
199 clock-frequency = <0>; /* Filled in by U-Boot */
200 current-speed = <0>; /* Filled in by U-Boot */
202 interrupts = <0x0 0x4>;
207 reg = <0xef600900 0x00000008>;
214 interrupts = <0x0 0x1>;
216 #address-cells = <0>;
217 #size-cells = <0>;
218 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
219 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
220 reg = <0xef600a00 0x00000070>;
223 mal-tx-channel = <0>;
224 mal-rx-channel = <0>;
225 cell-index = <0>;
231 phy-map = <0x00000000>;
233 rgmii-channel = <0>;
245 port = <0x0>; /* port number */
246 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
247 0x0000000c 0x10000000 0x00001000>; /* Registers */
248 dcr-reg = <0x100 0x020>;
249 sdr-base = <0x300>;
254 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
255 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
257 /* Inbound 2GB range starting at 0 */
258 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
260 /* This drives busses 10 to 0x1f */
261 bus-range = <0x10 0x1f>;
269 * The real slot is on idsel 0, so the swizzling is 1:1
271 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
273 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
274 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
275 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
276 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
286 port = <0x1>; /* port number */
287 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
288 0x0000000c 0x10001000 0x00001000>; /* Registers */
289 dcr-reg = <0x120 0x020>;
290 sdr-base = <0x340>;
295 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
296 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
298 /* Inbound 2GB range starting at 0 */
299 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
301 /* This drives busses 10 to 0x1f */
302 bus-range = <0x20 0x2f>;
310 * The real slot is on idsel 0, so the swizzling is 1:1
312 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
314 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
315 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
316 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
317 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
327 port = <0x2>; /* port number */
328 reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
329 0x0000000c 0x10002000 0x00001000>; /* Registers */
330 dcr-reg = <0x140 0x020>;
331 sdr-base = <0x370>;
336 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
337 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
339 /* Inbound 2GB range starting at 0 */
340 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
342 /* This drives busses 10 to 0x1f */
343 bus-range = <0x30 0x3f>;
351 * The real slot is on idsel 0, so the swizzling is 1:1
353 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
355 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
356 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
357 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
358 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;