Lines Matching +full:3 +full:- +full:cell
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>; // L1
34 i-cache-size = <32768>; // L1
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
49 #address-cells = <2>;
50 #size-cells = <1>;
51 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
54 interrupt-parent = <&mpic>;
61 3 0 0xe8000000 0x00000020>;
65 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
72 compatible = "cfi-flash";
74 bank-width = <2>;
75 device-width = <1>;
79 compatible = "fsl,mpc8610-fcm-nand",
80 "fsl,elbc-fcm-nand";
85 compatible = "fsl,mpc8610-fcm-nand",
86 "fsl,elbc-fcm-nand";
91 compatible = "fsl,mpc8610-fcm-nand",
92 "fsl,elbc-fcm-nand";
97 compatible = "fsl,mpc8610-fcm-nand",
98 "fsl,elbc-fcm-nand";
102 board-control@3,0 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,fpga-pixis";
106 reg = <3 0 0x20>;
107 ranges = <0 3 0 0x20>;
108 interrupt-parent = <&mpic>;
111 sdcsr_pio: gpio-controller@a {
112 #gpio-cells = <2>;
113 compatible = "fsl,fpga-pixis-gpio-bank";
115 gpio-controller;
121 #address-cells = <1>;
122 #size-cells = <1>;
123 #interrupt-cells = <2>;
125 compatible = "fsl,mpc8610-immr", "simple-bus";
127 bus-frequency = <0>;
129 mcm-law@0 {
130 compatible = "fsl,mcm-law";
132 fsl,num-laws = <10>;
136 compatible = "fsl,mpc8610-mcm", "fsl,mcm";
139 interrupt-parent = <&mpic>;
143 #address-cells = <1>;
144 #size-cells = <0>;
145 cell-index = <0>;
146 compatible = "fsl-i2c";
149 interrupt-parent = <&mpic>;
155 /* MCLK source is a stand-alone oscillator */
156 clock-frequency = <12288000>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 cell-index = <1>;
164 compatible = "fsl-i2c";
167 interrupt-parent = <&mpic>;
173 cell-index = <0>;
177 clock-frequency = <0>;
179 interrupt-parent = <&mpic>;
184 cell-index = <1>;
188 clock-frequency = <0>;
190 interrupt-parent = <&mpic>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,mpc8610-spi", "fsl,spi";
199 cell-index = <0>;
201 interrupt-parent = <&mpic>;
203 cs-gpios = <&sdcsr_pio 7 0>;
206 mmc-slot@0 {
207 compatible = "fsl,mpc8610hpcd-mmc-slot",
208 "mmc-spi-slot";
212 voltage-ranges = <3300 3300>;
213 spi-max-frequency = <50000000>;
221 interrupt-parent = <&mpic>;
225 mpic: interrupt-controller@40000 {
226 interrupt-controller;
227 #address-cells = <0>;
228 #interrupt-cells = <2>;
230 compatible = "chrp,open-pic";
231 device_type = "open-pic";
235 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
237 msi-available-ranges = <0 0x100>;
247 interrupt-parent = <&mpic>;
250 global-utilities@e0000 {
251 #address-cells = <1>;
252 #size-cells = <1>;
253 compatible = "fsl,mpc8610-guts";
256 fsl,has-rstcr;
259 compatible = "fsl,mpc8610-pmc",
260 "fsl,mpc8641d-pmc";
266 compatible = "fsl,mpc8610-wdt";
271 compatible = "fsl,mpc8610-ssi";
272 cell-index = <0>;
274 interrupt-parent = <&mpic>;
276 fsl,mode = "i2s-slave";
277 codec-handle = <&cs4270>;
278 fsl,playback-dma = <&dma00>;
279 fsl,capture-dma = <&dma01>;
280 fsl,fifo-depth = <8>;
285 compatible = "fsl,mpc8610-ssi";
287 cell-index = <1>;
289 interrupt-parent = <&mpic>;
291 fsl,fifo-depth = <8>;
296 #address-cells = <1>;
297 #size-cells = <1>;
298 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
299 cell-index = <0>;
304 dma00: dma-channel@0 {
305 compatible = "fsl,mpc8610-dma-channel",
306 "fsl,ssi-dma-channel";
307 cell-index = <0>;
309 interrupt-parent = <&mpic>;
312 dma01: dma-channel@1 {
313 compatible = "fsl,mpc8610-dma-channel",
314 "fsl,ssi-dma-channel";
315 cell-index = <1>;
317 interrupt-parent = <&mpic>;
320 dma-channel@2 {
321 compatible = "fsl,mpc8610-dma-channel",
322 "fsl,eloplus-dma-channel";
323 cell-index = <2>;
325 interrupt-parent = <&mpic>;
328 dma-channel@3 {
329 compatible = "fsl,mpc8610-dma-channel",
330 "fsl,eloplus-dma-channel";
331 cell-index = <3>;
333 interrupt-parent = <&mpic>;
339 #address-cells = <1>;
340 #size-cells = <1>;
341 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
342 cell-index = <1>;
347 dma-channel@0 {
348 compatible = "fsl,mpc8610-dma-channel",
349 "fsl,eloplus-dma-channel";
350 cell-index = <0>;
352 interrupt-parent = <&mpic>;
355 dma-channel@1 {
356 compatible = "fsl,mpc8610-dma-channel",
357 "fsl,eloplus-dma-channel";
358 cell-index = <1>;
360 interrupt-parent = <&mpic>;
363 dma-channel@2 {
364 compatible = "fsl,mpc8610-dma-channel",
365 "fsl,eloplus-dma-channel";
366 cell-index = <2>;
368 interrupt-parent = <&mpic>;
371 dma-channel@3 {
372 compatible = "fsl,mpc8610-dma-channel",
373 "fsl,eloplus-dma-channel";
374 cell-index = <3>;
376 interrupt-parent = <&mpic>;
384 compatible = "fsl,mpc8610-pci";
386 #interrupt-cells = <1>;
387 #size-cells = <2>;
388 #address-cells = <3>;
390 bus-range = <0 0>;
394 clock-frequency = <33333333>;
395 interrupt-parent = <&mpic>;
397 interrupt-map-mask = <0xf800 0 0 7>;
398 interrupt-map = <
402 0x8800 0 0 3 &mpic 6 1
408 0x9000 0 0 3 &mpic 7 1
414 compatible = "fsl,mpc8641-pcie";
416 #interrupt-cells = <1>;
417 #size-cells = <2>;
418 #address-cells = <3>;
420 bus-range = <1 3>;
424 clock-frequency = <33333333>;
425 interrupt-parent = <&mpic>;
427 interrupt-map-mask = <0xf800 0 0 7>;
429 interrupt-map = <
436 0xe000 0 0 3 &mpic 1 1
440 0xf800 0 0 1 &mpic 3 2
446 #size-cells = <2>;
447 #address-cells = <3>;
457 #size-cells = <2>;
458 #address-cells = <3>;
468 #size-cells = <1>;
469 #address-cells = <2>;
484 #address-cells = <3>;
485 #size-cells = <2>;
486 #interrupt-cells = <1>;
488 compatible = "fsl,mpc8641-pcie";
492 bus-range = <0 255>;
493 interrupt-map-mask = <0xf800 0 0 7>;
494 interrupt-map = <0x0000 0 0 1 &mpic 4 1
496 0x0000 0 0 3 &mpic 6 1
498 interrupt-parent = <&mpic>;
501 clock-frequency = <33333333>;