Lines Matching +full:0 +full:xc300
26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
55 ranges = <0 0 0xf8000000 0x08000000
56 1 0 0xf0000000 0x08000000
57 2 0 0xe8400000 0x00008000
58 4 0 0xe8440000 0x00008000
59 5 0 0xe8480000 0x00008000
60 6 0 0xe84c0000 0x00008000
61 3 0 0xe8000000 0x00000020>;
62 sleep = <&pmc 0x08000000 0>;
64 flash@0,0 {
66 reg = <0 0 0x8000000>;
71 flash@1,0 {
73 reg = <1 0 0x8000000>;
78 flash@2,0 {
81 reg = <2 0 0x8000>;
84 flash@4,0 {
87 reg = <4 0 0x8000>;
90 flash@5,0 {
93 reg = <5 0 0x8000>;
96 flash@6,0 {
99 reg = <6 0 0x8000>;
102 board-control@3,0 {
106 reg = <3 0 0x20>;
107 ranges = <0 3 0 0x20>;
114 reg = <0xa 1>;
126 ranges = <0x0 0xe0000000 0x00100000>;
127 bus-frequency = <0>;
129 mcm-law@0 {
131 reg = <0x0 0x1000>;
137 reg = <0x1000 0x1000>;
144 #size-cells = <0>;
145 cell-index = <0>;
147 reg = <0x3000 0x100>;
154 reg = <0x4f>;
162 #size-cells = <0>;
165 reg = <0x3100 0x100>;
168 sleep = <&pmc 0x00000004 0>;
173 cell-index = <0>;
176 reg = <0x4500 0x100>;
177 clock-frequency = <0>;
180 sleep = <&pmc 0x00000002 0>;
187 reg = <0x4600 0x100>;
188 clock-frequency = <0>;
191 sleep = <&pmc 0x00000008 0>;
196 #size-cells = <0>;
198 reg = <0x7000 0x40>;
199 cell-index = <0>;
203 cs-gpios = <&sdcsr_pio 7 0>;
204 sleep = <&pmc 0x00000800 0>;
206 mmc-slot@0 {
209 reg = <0>;
210 gpios = <&sdcsr_pio 0 1 /* nCD */
211 &sdcsr_pio 1 0>; /* WP */
219 reg = <0x2c000 100>;
222 sleep = <&pmc 0x04000000 0>;
227 #address-cells = <0>;
229 reg = <0x40000 0x40000>;
236 reg = <0x41600 0x80>;
237 msi-available-ranges = <0 0x100>;
239 0xe0 0
240 0xe1 0
241 0xe2 0
242 0xe3 0
243 0xe4 0
244 0xe5 0
245 0xe6 0
246 0xe7 0>;
254 reg = <0xe0000 0x1000>;
255 ranges = <0 0xe0000 0x1000>;
261 reg = <0x70 0x20>;
267 reg = <0xe4000 0x100>;
272 cell-index = <0>;
273 reg = <0x16000 0x100>;
281 sleep = <&pmc 0 0x08000000>;
288 reg = <0x16100 0x100>;
292 sleep = <&pmc 0 0x04000000>;
299 cell-index = <0>;
300 reg = <0x21300 0x4>; /* DMA general status register */
301 ranges = <0x0 0x21100 0x200>;
302 sleep = <&pmc 0x00000400 0>;
304 dma00: dma-channel@0 {
307 cell-index = <0>;
308 reg = <0x0 0x80>;
316 reg = <0x80 0x80>;
324 reg = <0x100 0x80>;
332 reg = <0x180 0x80>;
343 reg = <0xc300 0x4>; /* DMA general status register */
344 ranges = <0x0 0xc100 0x200>;
345 sleep = <&pmc 0x00000200 0>;
347 dma-channel@0 {
350 cell-index = <0>;
351 reg = <0x0 0x80>;
359 reg = <0x80 0x80>;
367 reg = <0x100 0x80>;
375 reg = <0x180 0x80>;
389 reg = <0xe0008000 0x1000>;
390 bus-range = <0 0>;
391 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
392 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
393 sleep = <&pmc 0x80000000 0>;
397 interrupt-map-mask = <0xf800 0 0 7>;
399 /* IDSEL 0x11 */
400 0x8800 0 0 1 &mpic 4 1
401 0x8800 0 0 2 &mpic 5 1
402 0x8800 0 0 3 &mpic 6 1
403 0x8800 0 0 4 &mpic 7 1
405 /* IDSEL 0x12 */
406 0x9000 0 0 1 &mpic 5 1
407 0x9000 0 0 2 &mpic 6 1
408 0x9000 0 0 3 &mpic 7 1
409 0x9000 0 0 4 &mpic 4 1
419 reg = <0xe000a000 0x1000>;
421 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
422 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
423 sleep = <&pmc 0x40000000 0>;
427 interrupt-map-mask = <0xf800 0 0 7>;
430 /* IDSEL 0x1b */
431 0xd800 0 0 1 &mpic 2 1
433 /* IDSEL 0x1c*/
434 0xe000 0 0 1 &mpic 1 1
435 0xe000 0 0 2 &mpic 1 1
436 0xe000 0 0 3 &mpic 1 1
437 0xe000 0 0 4 &mpic 1 1
439 /* IDSEL 0x1f */
440 0xf800 0 0 1 &mpic 3 2
441 0xf800 0 0 2 &mpic 0 1
444 pcie@0 {
445 reg = <0 0 0 0 0>;
449 ranges = <0x02000000 0x0 0xa0000000
450 0x02000000 0x0 0xa0000000
451 0x0 0x10000000
452 0x01000000 0x0 0x00000000
453 0x01000000 0x0 0x00000000
454 0x0 0x00100000>;
455 uli1575@0 {
456 reg = <0 0 0 0 0>;
459 ranges = <0x02000000 0x0 0xa0000000
460 0x02000000 0x0 0xa0000000
461 0x0 0x10000000
462 0x01000000 0x0 0x00000000
463 0x01000000 0x0 0x00000000
464 0x0 0x00100000>;
470 reg = <0xf000 0 0 0 0>;
471 ranges = <1 0 0x01000000 0 0
472 0x00001000>;
476 reg = <1 0x70 2>;
489 reg = <0xe0009000 0x00001000>;
490 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
491 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
492 bus-range = <0 255>;
493 interrupt-map-mask = <0xf800 0 0 7>;
494 interrupt-map = <0x0000 0 0 1 &mpic 4 1
495 0x0000 0 0 2 &mpic 5 1
496 0x0000 0 0 3 &mpic 6 1
497 0x0000 0 0 4 &mpic 7 1>;
500 sleep = <&pmc 0x20000000 0>;