Lines Matching +full:0 +full:x8
31 #size-cells = <0>;
33 PowerPC,8360@0 {
35 reg = <0x0>;
48 reg = <0x00000000 0x10000000>;
56 reg = <0xe0005000 0xd8>;
57 ranges = <0 0 0xfe000000 0x02000000
58 1 0 0xf8000000 0x00008000>;
60 flash@0,0 {
62 reg = <0 0 0x2000000>;
67 bcsr@1,0 {
71 reg = <1 0 0x8000>;
72 ranges = <0 1 0 0x8000>;
77 reg = <0xd 1>;
88 ranges = <0x0 0xe0000000 0x00100000>;
89 reg = <0xe0000000 0x00000200>;
95 reg = <0x200 0x100>;
100 reg = <0xb00 0x100 0xa00 0x100>;
101 interrupts = <80 0x8>;
107 #size-cells = <0>;
108 cell-index = <0>;
110 reg = <0x3000 0x100>;
111 interrupts = <14 0x8>;
117 reg = <0x68>;
123 #size-cells = <0>;
126 reg = <0x3100 0x100>;
127 interrupts = <15 0x8>;
133 cell-index = <0>;
136 reg = <0x4500 0x100>;
138 interrupts = <9 0x8>;
146 reg = <0x4600 0x100>;
148 interrupts = <10 0x8>;
156 reg = <0x82a8 4>;
157 ranges = <0 0x8100 0x1a8>;
160 cell-index = <0>;
161 dma-channel@0 {
163 reg = <0 0x80>;
164 cell-index = <0>;
170 reg = <0x80 0x80>;
177 reg = <0x100 0x80>;
184 reg = <0x180 0x28>;
192 compatible = "fsl,sec2.0";
193 reg = <0x30000 0x10000>;
194 interrupts = <11 0x8>;
198 fsl,exec-units-mask = <0x7e>;
199 fsl,descriptor-types-mask = <0x01010ebf>;
200 sleep = <&pmc 0x03000000>;
205 #address-cells = <0>;
207 reg = <0x700 0x100>;
214 reg = <0x1400 0x100>;
215 ranges = <0 0x1400 0x100>;
223 reg = <0x18 0x18>;
230 0 3 1 0 1 0 /* TxD0 */
231 0 4 1 0 1 0 /* TxD1 */
232 0 5 1 0 1 0 /* TxD2 */
233 0 6 1 0 1 0 /* TxD3 */
234 1 6 1 0 3 0 /* TxD4 */
235 1 7 1 0 1 0 /* TxD5 */
236 1 9 1 0 2 0 /* TxD6 */
237 1 10 1 0 2 0 /* TxD7 */
238 0 9 2 0 1 0 /* RxD0 */
239 0 10 2 0 1 0 /* RxD1 */
240 0 11 2 0 1 0 /* RxD2 */
241 0 12 2 0 1 0 /* RxD3 */
242 0 13 2 0 1 0 /* RxD4 */
243 1 1 2 0 2 0 /* RxD5 */
244 1 0 2 0 2 0 /* RxD6 */
245 1 4 2 0 2 0 /* RxD7 */
246 0 7 1 0 1 0 /* TX_EN */
247 0 8 1 0 1 0 /* TX_ER */
248 0 15 2 0 1 0 /* RX_DV */
249 0 16 2 0 1 0 /* RX_ER */
250 0 0 2 0 1 0 /* RX_CLK */
251 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
252 2 8 2 0 1 0>; /* GTX125 - CLK9 */
257 0 17 1 0 1 0 /* TxD0 */
258 0 18 1 0 1 0 /* TxD1 */
259 0 19 1 0 1 0 /* TxD2 */
260 0 20 1 0 1 0 /* TxD3 */
261 1 2 1 0 1 0 /* TxD4 */
262 1 3 1 0 2 0 /* TxD5 */
263 1 5 1 0 3 0 /* TxD6 */
264 1 8 1 0 3 0 /* TxD7 */
265 0 23 2 0 1 0 /* RxD0 */
266 0 24 2 0 1 0 /* RxD1 */
267 0 25 2 0 1 0 /* RxD2 */
268 0 26 2 0 1 0 /* RxD3 */
269 0 27 2 0 1 0 /* RxD4 */
270 1 12 2 0 2 0 /* RxD5 */
271 1 13 2 0 3 0 /* RxD6 */
272 1 11 2 0 2 0 /* RxD7 */
273 0 21 1 0 1 0 /* TX_EN */
274 0 22 1 0 1 0 /* TX_ER */
275 0 29 2 0 1 0 /* RX_DV */
276 0 30 2 0 1 0 /* RX_ER */
277 0 31 2 0 1 0 /* RX_CLK */
278 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
279 2 3 2 0 1 0 /* GTX125 - CLK4 */
280 0 1 3 0 2 0 /* MDIO */
281 0 2 1 0 1 0>; /* MDC */
292 ranges = <0x0 0xe0100000 0x00100000>;
293 reg = <0xe0100000 0x480>;
294 brg-frequency = <0>;
303 ranges = <0x0 0x00010000 0x0000c000>;
305 data-only@0 {
308 reg = <0x0 0xc000>;
315 reg = <0x440 0x40>;
322 cell-index = <0>;
324 reg = <0x4c0 0x40>;
333 reg = <0x500 0x40>;
342 reg = <0x6c0 0x40 0x8b00 0x100>;
347 gpios = <&qe_pio_b 2 0 /* USBOE */
348 &qe_pio_b 3 0 /* USBTP */
349 &qe_pio_b 8 0 /* USBTN */
350 &qe_pio_b 9 0 /* USBRP */
351 &qe_pio_b 11 0 /* USBRN */
352 &bcsr13 5 0 /* SPEED */
360 reg = <0x2000 0x200>;
375 reg = <0x3000 0x200>;
388 #size-cells = <0>;
389 reg = <0x2120 0x18>;
392 phy0: ethernet-phy@0 {
394 interrupts = <17 0x8>;
395 reg = <0x0>;
399 interrupts = <18 0x8>;
400 reg = <0x1>;
404 reg = <0x2>;
411 #address-cells = <0>;
413 reg = <0x80 0x80>;
415 interrupts = <32 0x8 33 0x8>; // high:32 low:33
421 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
424 /* IDSEL 0x11 AD17 */
425 0x8800 0x0 0x0 0x1 &ipic 20 0x8
426 0x8800 0x0 0x0 0x2 &ipic 21 0x8
427 0x8800 0x0 0x0 0x3 &ipic 22 0x8
428 0x8800 0x0 0x0 0x4 &ipic 23 0x8
430 /* IDSEL 0x12 AD18 */
431 0x9000 0x0 0x0 0x1 &ipic 22 0x8
432 0x9000 0x0 0x0 0x2 &ipic 23 0x8
433 0x9000 0x0 0x0 0x3 &ipic 20 0x8
434 0x9000 0x0 0x0 0x4 &ipic 21 0x8
436 /* IDSEL 0x13 AD19 */
437 0x9800 0x0 0x0 0x1 &ipic 23 0x8
438 0x9800 0x0 0x0 0x2 &ipic 20 0x8
439 0x9800 0x0 0x0 0x3 &ipic 21 0x8
440 0x9800 0x0 0x0 0x4 &ipic 22 0x8
442 /* IDSEL 0x15 AD21*/
443 0xa800 0x0 0x0 0x1 &ipic 20 0x8
444 0xa800 0x0 0x0 0x2 &ipic 21 0x8
445 0xa800 0x0 0x0 0x3 &ipic 22 0x8
446 0xa800 0x0 0x0 0x4 &ipic 23 0x8
448 /* IDSEL 0x16 AD22*/
449 0xb000 0x0 0x0 0x1 &ipic 23 0x8
450 0xb000 0x0 0x0 0x2 &ipic 20 0x8
451 0xb000 0x0 0x0 0x3 &ipic 21 0x8
452 0xb000 0x0 0x0 0x4 &ipic 22 0x8
454 /* IDSEL 0x17 AD23*/
455 0xb800 0x0 0x0 0x1 &ipic 22 0x8
456 0xb800 0x0 0x0 0x2 &ipic 23 0x8
457 0xb800 0x0 0x0 0x3 &ipic 20 0x8
458 0xb800 0x0 0x0 0x4 &ipic 21 0x8
460 /* IDSEL 0x18 AD24*/
461 0xc000 0x0 0x0 0x1 &ipic 21 0x8
462 0xc000 0x0 0x0 0x2 &ipic 22 0x8
463 0xc000 0x0 0x0 0x3 &ipic 23 0x8
464 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
466 interrupts = <66 0x8>;
467 bus-range = <0 0>;
468 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
469 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
470 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
475 reg = <0xe0008500 0x100 /* internal registers */
476 0xe0008300 0x8>; /* config space access registers */
479 sleep = <&pmc 0x00010000>;