Lines Matching +full:0 +full:x2200
26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
52 reg = <0xe0000000 0x00000200>;
53 bus-frequency = <0>;
58 reg = <0x200 0x100>;
63 reg = <0xb00 0x100 0xa00 0x100>;
64 interrupts = <80 0x8>;
70 #size-cells = <0>;
71 cell-index = <0>;
73 reg = <0x3000 0x100>;
74 interrupts = <14 0x8>;
80 cell-index = <0>;
83 reg = <0x4500 0x100>;
84 clock-frequency = <0>;
85 interrupts = <9 0x8>;
93 reg = <0x4600 0x100>;
94 clock-frequency = <0>;
95 interrupts = <10 0x8>;
103 reg = <0x82a8 4>;
104 ranges = <0 0x8100 0x1a8>;
107 cell-index = <0>;
108 dma-channel@0 {
110 reg = <0 0x80>;
111 cell-index = <0>;
117 reg = <0x80 0x80>;
124 reg = <0x100 0x80>;
131 reg = <0x180 0x28>;
139 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
140 reg = <0x30000 0x10000>;
141 interrupts = <11 0x8>;
145 fsl,exec-units-mask = <0x4c>;
146 fsl,descriptor-types-mask = <0x0122003f>;
147 sleep = <&pmc 0x03000000>;
152 #address-cells = <0>;
154 reg = <0x700 0x100>;
161 reg = <0x1400 0x100>;
162 ranges = <3 0x1448 0x18>;
170 reg = <3 0x18>;
177 3 4 3 0 2 0 /* MDIO */
178 3 5 1 0 2 0 /* MDC */
179 3 21 2 0 1 0 /* RX_CLK (CLK16) */
180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
181 0 18 1 0 1 0 /* TxD0 */
182 0 19 1 0 1 0 /* TxD1 */
183 0 20 1 0 1 0 /* TxD2 */
184 0 21 1 0 1 0 /* TxD3 */
185 0 22 2 0 1 0 /* RxD0 */
186 0 23 2 0 1 0 /* RxD1 */
187 0 24 2 0 1 0 /* RxD2 */
188 0 25 2 0 1 0 /* RxD3 */
189 0 26 2 0 1 0 /* RX_ER */
190 0 27 1 0 1 0 /* TX_ER */
191 0 28 2 0 1 0 /* RX_DV */
192 0 29 2 0 1 0 /* COL */
193 0 30 1 0 1 0 /* TX_EN */
194 0 31 2 0 1 0>; /* CRS */
199 0 13 2 0 1 0 /* RX_CLK (CLK9) */
200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
201 1 0 1 0 1 0 /* TxD0 */
202 1 1 1 0 1 0 /* TxD1 */
203 1 2 1 0 1 0 /* TxD2 */
204 1 3 1 0 1 0 /* TxD3 */
205 1 4 2 0 1 0 /* RxD0 */
206 1 5 2 0 1 0 /* RxD1 */
207 1 6 2 0 1 0 /* RxD2 */
208 1 7 2 0 1 0 /* RxD3 */
209 1 8 2 0 1 0 /* RX_ER */
210 1 9 1 0 1 0 /* TX_ER */
211 1 10 2 0 1 0 /* RX_DV */
212 1 11 2 0 1 0 /* COL */
213 1 12 1 0 1 0 /* TX_EN */
214 1 13 2 0 1 0>; /* CRS */
224 ranges = <0x0 0xe0100000 0x00100000>;
225 reg = <0xe0100000 0x480>;
226 brg-frequency = <0>;
235 ranges = <0x0 0x00010000 0x00004000>;
237 data-only@0 {
240 reg = <0x0 0x4000>;
246 #size-cells = <0>;
247 cell-index = <0>;
249 reg = <0x4c0 0x40>;
252 cs-gpios = <&qe_pio_d 13 0>;
255 mmc-slot@0 {
258 reg = <0>;
260 &qe_pio_d 15 0>;
269 reg = <0x500 0x40>;
279 reg = <0x3000 0x200>;
293 reg = <0x2200 0x200>;
305 #size-cells = <0>;
306 reg = <0x3120 0x18>;
309 phy00:ethernet-phy@0 {
310 reg = <0x0>;
313 reg = <0x4>;
320 #address-cells = <0>;
322 reg = <0x80 0x80>;
324 interrupts = <32 0x8 33 0x8>; //high:32 low:33
330 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
332 /* IDSEL 0x10 AD16 (USB) */
333 0x8000 0x0 0x0 0x1 &ipic 17 0x8
335 /* IDSEL 0x11 AD17 (Mini1)*/
336 0x8800 0x0 0x0 0x1 &ipic 18 0x8
337 0x8800 0x0 0x0 0x2 &ipic 19 0x8
338 0x8800 0x0 0x0 0x3 &ipic 20 0x8
339 0x8800 0x0 0x0 0x4 &ipic 48 0x8
341 /* IDSEL 0x12 AD18 (PCI/Mini2) */
342 0x9000 0x0 0x0 0x1 &ipic 19 0x8
343 0x9000 0x0 0x0 0x2 &ipic 20 0x8
344 0x9000 0x0 0x0 0x3 &ipic 48 0x8
345 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
348 interrupts = <66 0x8>;
349 bus-range = <0x0 0x0>;
350 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
351 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
352 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
353 clock-frequency = <0>;
357 reg = <0xe0008500 0x100 /* internal registers */
358 0xe0008300 0x8>; /* config space access registers */
361 sleep = <&pmc 0x00010000>;