Lines Matching +full:0 +full:x2200
39 #size-cells = <0>;
41 PowerPC,8323@0 {
43 reg = <0x0>;
48 timebase-frequency = <0>;
49 bus-frequency = <0>;
50 clock-frequency = <0>;
56 reg = <0x00000000 0x08000000>;
61 reg = <0xf8000000 0x8000>;
69 ranges = <0x0 0xe0000000 0x00100000>;
70 reg = <0xe0000000 0x00000200>;
76 reg = <0x200 0x100>;
81 reg = <0xb00 0x100 0xa00 0x100>;
82 interrupts = <80 0x8>;
88 #size-cells = <0>;
89 cell-index = <0>;
91 reg = <0x3000 0x100>;
92 interrupts = <14 0x8>;
98 reg = <0x68>;
103 cell-index = <0>;
106 reg = <0x4500 0x100>;
107 clock-frequency = <0>;
108 interrupts = <9 0x8>;
116 reg = <0x4600 0x100>;
117 clock-frequency = <0>;
118 interrupts = <10 0x8>;
126 reg = <0x82a8 4>;
127 ranges = <0 0x8100 0x1a8>;
130 cell-index = <0>;
131 dma-channel@0 {
133 reg = <0 0x80>;
134 cell-index = <0>;
140 reg = <0x80 0x80>;
147 reg = <0x100 0x80>;
154 reg = <0x180 0x28>;
162 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
163 reg = <0x30000 0x10000>;
164 interrupts = <11 0x8>;
168 fsl,exec-units-mask = <0x4c>;
169 fsl,descriptor-types-mask = <0x0122003f>;
170 sleep = <&pmc 0x03000000>;
175 #address-cells = <0>;
177 reg = <0x700 0x100>;
182 reg = <0x1400 0x100>;
189 3 4 3 0 2 0 /* MDIO */
190 3 5 1 0 2 0 /* MDC */
191 0 13 2 0 1 0 /* RX_CLK (CLK9) */
192 3 24 2 0 1 0 /* TX_CLK (CLK10) */
193 1 0 1 0 1 0 /* TxD0 */
194 1 1 1 0 1 0 /* TxD1 */
195 1 2 1 0 1 0 /* TxD2 */
196 1 3 1 0 1 0 /* TxD3 */
197 1 4 2 0 1 0 /* RxD0 */
198 1 5 2 0 1 0 /* RxD1 */
199 1 6 2 0 1 0 /* RxD2 */
200 1 7 2 0 1 0 /* RxD3 */
201 1 8 2 0 1 0 /* RX_ER */
202 1 9 1 0 1 0 /* TX_ER */
203 1 10 2 0 1 0 /* RX_DV */
204 1 11 2 0 1 0 /* COL */
205 1 12 1 0 1 0 /* TX_EN */
206 1 13 2 0 1 0>; /* CRS */
211 3 31 2 0 1 0 /* RX_CLK (CLK7) */
212 3 6 2 0 1 0 /* TX_CLK (CLK8) */
213 1 18 1 0 1 0 /* TxD0 */
214 1 19 1 0 1 0 /* TxD1 */
215 1 20 1 0 1 0 /* TxD2 */
216 1 21 1 0 1 0 /* TxD3 */
217 1 22 2 0 1 0 /* RxD0 */
218 1 23 2 0 1 0 /* RxD1 */
219 1 24 2 0 1 0 /* RxD2 */
220 1 25 2 0 1 0 /* RxD3 */
221 1 26 2 0 1 0 /* RX_ER */
222 1 27 1 0 1 0 /* TX_ER */
223 1 28 2 0 1 0 /* RX_DV */
224 1 29 2 0 1 0 /* COL */
225 1 30 1 0 1 0 /* TX_EN */
226 1 31 2 0 1 0>; /* CRS */
234 2 0 1 0 2 0 /* TxD5 */
235 2 8 2 0 2 0 /* RxD5 */
237 2 29 2 0 0 0 /* CTS5 */
238 2 31 1 0 2 0 /* RTS5 */
240 2 24 2 0 0 0 /* CD */
253 ranges = <0x0 0xe0100000 0x00100000>;
254 reg = <0xe0100000 0x480>;
255 brg-frequency = <0>;
264 ranges = <0x0 0x00010000 0x00004000>;
266 data-only@0 {
269 reg = <0x0 0x4000>;
274 cell-index = <0>;
276 reg = <0x4c0 0x40>;
285 reg = <0x500 0x40>;
293 reg = <0x6c0 0x40 0x8b00 0x100>;
303 reg = <0x2200 0x200>;
317 reg = <0x3200 0x200>;
331 port-number = <0>; /* Which ttyQEx device */
333 reg = <0x2400 0x200>;
348 #size-cells = <0>;
349 reg = <0x2320 0x18>;
354 interrupts = <17 0x8>;
355 reg = <0x3>;
359 interrupts = <18 0x8>;
360 reg = <0x4>;
367 #address-cells = <0>;
369 reg = <0x80 0x80>;
371 interrupts = <32 0x8 33 0x8>; //high:32 low:33
377 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
379 /* IDSEL 0x11 AD17 */
380 0x8800 0x0 0x0 0x1 &ipic 20 0x8
381 0x8800 0x0 0x0 0x2 &ipic 21 0x8
382 0x8800 0x0 0x0 0x3 &ipic 22 0x8
383 0x8800 0x0 0x0 0x4 &ipic 23 0x8
385 /* IDSEL 0x12 AD18 */
386 0x9000 0x0 0x0 0x1 &ipic 22 0x8
387 0x9000 0x0 0x0 0x2 &ipic 23 0x8
388 0x9000 0x0 0x0 0x3 &ipic 20 0x8
389 0x9000 0x0 0x0 0x4 &ipic 21 0x8
391 /* IDSEL 0x13 AD19 */
392 0x9800 0x0 0x0 0x1 &ipic 23 0x8
393 0x9800 0x0 0x0 0x2 &ipic 20 0x8
394 0x9800 0x0 0x0 0x3 &ipic 21 0x8
395 0x9800 0x0 0x0 0x4 &ipic 22 0x8
397 /* IDSEL 0x15 AD21*/
398 0xa800 0x0 0x0 0x1 &ipic 20 0x8
399 0xa800 0x0 0x0 0x2 &ipic 21 0x8
400 0xa800 0x0 0x0 0x3 &ipic 22 0x8
401 0xa800 0x0 0x0 0x4 &ipic 23 0x8
403 /* IDSEL 0x16 AD22*/
404 0xb000 0x0 0x0 0x1 &ipic 23 0x8
405 0xb000 0x0 0x0 0x2 &ipic 20 0x8
406 0xb000 0x0 0x0 0x3 &ipic 21 0x8
407 0xb000 0x0 0x0 0x4 &ipic 22 0x8
409 /* IDSEL 0x17 AD23*/
410 0xb800 0x0 0x0 0x1 &ipic 22 0x8
411 0xb800 0x0 0x0 0x2 &ipic 23 0x8
412 0xb800 0x0 0x0 0x3 &ipic 20 0x8
413 0xb800 0x0 0x0 0x4 &ipic 21 0x8
415 /* IDSEL 0x18 AD24*/
416 0xc000 0x0 0x0 0x1 &ipic 21 0x8
417 0xc000 0x0 0x0 0x2 &ipic 22 0x8
418 0xc000 0x0 0x0 0x3 &ipic 23 0x8
419 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
421 interrupts = <66 0x8>;
422 bus-range = <0x0 0x0>;
423 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
424 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
425 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
426 clock-frequency = <0>;
430 reg = <0xe0008500 0x100 /* internal registers */
431 0xe0008300 0x8>; /* config space access registers */
434 sleep = <&pmc 0x00010000>;