Lines Matching +full:0 +full:xb00
26 #size-cells = <0>;
28 PowerPC,8313@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
58 0x1 0x0 0xe2800000 0x00008000
59 0x2 0x0 0xf0000000 0x00020000
60 0x3 0x0 0xfa000000 0x00008000>;
62 flash@0,0 {
66 reg = <0x0 0x0 0x800000>;
71 nand@1,0 {
76 reg = <0x1 0x0 0x2000>;
78 u-boot@0 {
79 reg = <0x0 0x100000>;
84 reg = <0x100000 0x300000>;
88 reg = <0x400000 0x1c00000>;
98 ranges = <0x0 0xe0000000 0x00100000>;
99 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>;
105 reg = <0x200 0x100>;
112 sleep = <&pmc 0x03000000>;
117 #size-cells = <0>;
118 cell-index = <0>;
120 reg = <0x3000 0x100>;
121 interrupts = <14 0x8>;
126 reg = <0x68>;
132 "fsl,sec2.0";
133 reg = <0x30000 0x10000>;
134 interrupts = <11 0x8>;
138 fsl,exec-units-mask = <0x4c>;
139 fsl,descriptor-types-mask = <0x0122003f>;
145 #size-cells = <0>;
148 reg = <0x3100 0x100>;
149 interrupts = <15 0x8>;
155 cell-index = <0>;
157 reg = <0x7000 0x1000>;
158 interrupts = <16 0x8>;
166 reg = <0x23000 0x1000>;
168 #size-cells = <0>;
170 interrupts = <38 0x8>;
172 sleep = <&pmc 0x00300000>;
177 reg = <0x24E00 0xB0>;
178 interrupts = <12 0x8 13 0x8>;
182 fsl,tmr-add = <0x999999A4>;
183 fsl,tmr-fiper1 = <0x3B9AC9F6>;
184 fsl,tmr-fiper2 = <0x00018696>;
191 sleep = <&pmc 0x20000000>;
192 ranges = <0x0 0x24000 0x1000>;
194 cell-index = <0>;
198 reg = <0x24000 0x1000>;
200 interrupts = <37 0x8 36 0x8 35 0x8>;
204 fixed-link = <1 1 1000 0 0>;
209 #size-cells = <0>;
211 reg = <0x520 0x20>;
214 interrupts = <20 0x8>;
215 reg = <0x4>;
218 reg = <0x11>;
231 reg = <0x25000 0x1000>;
232 ranges = <0x0 0x25000 0x1000>;
234 interrupts = <34 0x8 33 0x8 32 0x8>;
238 sleep = <&pmc 0x10000000>;
243 #size-cells = <0>;
245 reg = <0x520 0x20>;
248 reg = <0x11>;
257 cell-index = <0>;
260 reg = <0x4500 0x100>;
261 clock-frequency = <0>;
262 interrupts = <9 0x8>;
270 reg = <0x4600 0x100>;
271 clock-frequency = <0>;
272 interrupts = <10 0x8>;
284 #address-cells = <0>;
286 reg = <0x700 0x100>;
292 reg = <0xb00 0x100 0xa00 0x100>;
308 reg = <0x500 0x100>;
315 reg = <0x600 0x100>;
325 sleep = <&pmc 0x00010000>;
330 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
332 /* IDSEL 0x0E -mini PCI */
333 0x7000 0x0 0x0 0x1 &ipic 18 0x8
334 0x7000 0x0 0x0 0x2 &ipic 18 0x8
335 0x7000 0x0 0x0 0x3 &ipic 18 0x8
336 0x7000 0x0 0x0 0x4 &ipic 18 0x8
338 /* IDSEL 0x0F - PCI slot */
339 0x7800 0x0 0x0 0x1 &ipic 17 0x8
340 0x7800 0x0 0x0 0x2 &ipic 18 0x8
341 0x7800 0x0 0x0 0x3 &ipic 17 0x8
342 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
344 interrupts = <66 0x8>;
345 bus-range = <0x0 0x0>;
346 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
347 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
348 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
353 reg = <0xe0008500 0x100 /* internal registers */
354 0xe0008300 0x8>; /* config space access registers */
363 reg = <0xe00082a8 4>;
364 ranges = <0 0xe0008100 0x1a8>;
368 dma-channel@0 {
371 reg = <0 0x28>;
374 cell-index = <0>;
380 reg = <0x80 0x28>;
389 reg = <0x100 0x28>;
398 reg = <0x180 0x28>;