Lines Matching +full:0 +full:x7400
29 #size-cells =<0>;
31 PowerPC,7448@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 clock-frequency = <0>; // From U-Boot
40 bus-frequency = <0>; // From U-Boot
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
55 reg = <0xc0000000 0x10000>;
56 bus-frequency = <0>;
60 interrupts = <14 0>;
61 reg = <0x7000 0x400>;
68 reg = <0x6000 0x50>;
70 #size-cells = <0>;
75 reg = <0x8>;
81 reg = <0x9>;
87 linux,network-index = <0>;
88 #size-cells = <0>;
91 reg = <0x6000 0x200>;
102 #size-cells = <0>;
105 reg = <0x6400 0x200>;
116 reg = <0x7808 0x200>;
118 interrupts = <12 0>;
125 reg = <0x7c08 0x200>;
127 interrupts = <13 0>;
133 #address-cells = <0>;
135 reg = <0x7400 0x400>;
145 reg = <0x1000 0x1000>;
146 bus-range = <0 0>;
147 ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
148 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
152 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
155 /* IDSEL 0x11 */
156 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
157 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
158 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
159 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
161 /* IDSEL 0x12 */
162 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
163 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
164 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
165 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
167 /* IDSEL 0x13 */
168 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
169 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
170 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
171 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
173 /* IDSEL 0x14 */
174 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
175 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
176 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
177 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
181 clock-frequency = <0>;
184 #address-cells = <0>;