Lines Matching +full:0 +full:x0d0

16 	dcr-parent = <&{/cpus/cpu@0}>;
25 		#size-cells = <0>;
27 		cpu@0 {
30 			reg = <0x00000000>;
44 		reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
50 		cell-index = <0>;
51 		dcr-reg = <0x0c0 0x010>;
52 		#address-cells = <0>;
53 		#size-cells = <0>;
61 		dcr-reg = <0x0d0 0x010>;
62 		#address-cells = <0>;
63 		#size-cells = <0>;
65 		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
73 		dcr-reg = <0x0e0 0x010>;
74 		#address-cells = <0>;
75 		#size-cells = <0>;
77 		interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
85 		dcr-reg = <0x0f0 0x010>;
86 		#address-cells = <0>;
87 		#size-cells = <0>;
89 		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
98 		clock-frequency = <0>; /* Filled in by U-Boot */
102 			dcr-reg = <0x010 0x002>;
107 			dcr-reg = <0x180 0x062>;
110 			#address-cells = <0>;
111 			#size-cells = <0>;
113 			interrupts = </*TXEOB*/   0x6 0x4
114 					/*RXEOB*/ 0x7 0x4
115 					/*SERR*/  0x1 0x4
116 					/*TXDE*/  0x2 0x4
117 					/*RXDE*/  0x3 0x4>;
124 			ranges = <0x20000000 0x20000000 0x30000000
125 				  0x50000000 0x50000000 0x10000000
126 				  0x60000000 0x60000000 0x10000000
127 				  0xFE000000 0xFE000000 0x00010000>;
128 			dcr-reg = <0x100 0x020>;
133 				reg = <0x400a2000 0x00000010>;
139 				reg = <0x400a3000 0x100>;
144 				reg = <0x400a4000 0x100>;
150 				interrupts = <0x0>;
152 				#address-cells = <0>;
153 				#size-cells = <0>;
154 				interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
155 				reg = <0x400a0000 0x00000100>;
158 				mal-tx-channel = <0x0>;
159 				mal-rx-channel = <0x0>;
160 				cell-index = <0>;
165 				phy-address = <0x2>;
167 				phy-map = <0x00000000>;
169 				rgmii-channel = <0>;
171 				tah-channel = <0>;
180 				interrupts = <0x0>;
182 				#address-cells = <0>;
183 				#size-cells = <0>;
184 				interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
185 				reg = <0x400a1000 0x00000100>;
195 				phy-address = <0x3>;
197 				phy-map = <0x00000000>;
201 				tah-channel = <0>;