Lines Matching +full:0 +full:xe0010000
18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
65 dcr-reg = <0x0d0 0x009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
77 dcr-reg = <0x0e0 0x009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
81 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
88 dcr-reg = <0x0b0 0x003>;
89 unused-units = <0x00000000>;
90 idle-doze = <0x02000000>;
91 standby = <0xe3e74800>;
99 clock-frequency = <0>; /* Filled in by U-Boot */
103 dcr-reg = <0x010 0x002>;
105 interrupts = <0x5 0x4 /* ECC DED Error */
106 0x6 0x4>; /* ECC SEC Error */
111 reg = <0xef700000 0x80400>;
113 interrupts = <0x17 0x2>;
118 dcr-reg = <0x180 0x062>;
122 interrupts = <0x0 0x1 0x2 0x3 0x4>;
124 #address-cells = <0>;
125 #size-cells = <0>;
126 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
127 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
128 /*SERR*/ 0x2 &UIC1 0x0 0x4
129 /*TXDE*/ 0x3 &UIC1 0x1 0x4
130 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
131 interrupt-map-mask = <0xffffffff>;
138 ranges = <0x80000000 0x80000000 0x10000000
139 0xef600000 0xef600000 0x00a00000
140 0xf0000000 0xf0000000 0x10000000>;
141 dcr-reg = <0x0a0 0x005>;
142 clock-frequency = <0>; /* Filled in by U-Boot */
146 dcr-reg = <0x012 0x002>;
149 clock-frequency = <0>; /* Filled in by U-Boot */
151 interrupts = <0x5 0x1>;
154 nor_flash@0,0 {
157 reg = <0x00000000 0x00000000 0x04000000>;
160 partition@0 {
162 reg = <0x00000000 0x001e0000>;
166 reg = <0x001e0000 0x00020000>;
170 reg = <0x00200000 0x00200000>;
174 reg = <0x00400000 0x03b60000>;
178 reg = <0x03f60000 0x00040000>;
182 reg = <0x03fa0000 0x00060000>;
186 ndfc@1,0 {
188 reg = <0x00000001 0x00000000 0x00002000>;
189 ccr = <0x00001000>;
190 bank-settings = <0x80002222>;
198 partition@0 {
200 reg = <0x00000000 0x00100000>;
204 reg = <0x00000000 0x03f00000>;
213 reg = <0xef600200 0x00000008>;
214 virtual-reg = <0xef600200>;
215 clock-frequency = <0>; /* Filled in by U-Boot */
216 current-speed = <0>;
218 interrupts = <0x1a 0x4>;
224 reg = <0xef600300 0x00000008>;
225 virtual-reg = <0xef600300>;
226 clock-frequency = <0>; /* Filled in by U-Boot */
227 current-speed = <0>;
229 interrupts = <0x1 0x4>;
234 reg = <0xef600400 0x00000014>;
236 interrupts = <0x2 0x4>;
238 #size-cells = <0>;
242 reg = <0x68>;
247 reg = <0x48>;
253 reg = <0xef600500 0x00000014>;
255 interrupts = <0x7 0x4>;
260 reg = <0xef600b00 0x00000104>;
265 linux,network-index = <0x0>;
269 interrupts = <0x0 0x1>;
271 #address-cells = <0>;
272 #size-cells = <0>;
273 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
274 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
275 reg = <0xef600900 0x000000c4>;
278 mal-tx-channel = <0>;
279 mal-rx-channel = <0>;
280 cell-index = <0>;
287 phy-map = <0x00000000>;
289 rgmii-channel = <0>;
295 linux,network-index = <0x1>;
299 interrupts = <0x0 0x1>;
301 #address-cells = <0>;
302 #size-cells = <0>;
303 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
304 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
305 reg = <0xef600a00 0x000000c4>;
317 phy-map = <0x00000000>;
332 port = <0x0>; /* port number */
333 reg = <0xa0000000 0x20000000 /* Config space access */
334 0xef000000 0x00001000>; /* Registers */
335 dcr-reg = <0x040 0x020>;
336 sdr-base = <0x400>;
341 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
342 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
344 /* Inbound 2GB range starting at 0 */
345 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
347 /* This drives busses 0x00 to 0x3f */
348 bus-range = <0x0 0x3f>;
356 * The real slot is on idsel 0, so the swizzling is 1:1
358 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
360 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
361 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
362 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
363 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
373 port = <0x1>; /* port number */
374 reg = <0xc0000000 0x20000000 /* Config space access */
375 0xef001000 0x00001000>; /* Registers */
376 dcr-reg = <0x060 0x020>;
377 sdr-base = <0x440>;
382 ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
383 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
385 /* Inbound 2GB range starting at 0 */
386 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
388 /* This drives busses 0x40 to 0x7f */
389 bus-range = <0x40 0x7f>;
397 * The real slot is on idsel 0, so the swizzling is 1:1
399 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
401 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
402 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
403 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
404 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;