Lines Matching +full:cache +full:- +full:controller +full:- +full:0

15 /dts-v1/;
17 /memreserve/ 0x01f00000 0x00100000;
20 	#address-cells = <2>;
21 	#size-cells = <1>;
22 	model = "ibm,iss-4xx";
23 	compatible = "ibm,iss-4xx";
24 	dcr-parent = <&{/cpus/cpu@0}>;
31 		#address-cells = <1>;
32 		#size-cells = <0>;
34 		cpu@0 {
37 			reg = <0>;
38 			clock-frequency = <100000000>; // 100Mhz :-)
39 			timebase-frequency = <100000000>;
40 			i-cache-line-size = <32>;
41 			d-cache-line-size = <32>;
42 			i-cache-size = <32768>;
43 			d-cache-size = <32768>;
44 			dcr-controller;
45 			dcr-access-method = "native";
52 			clock-frequency = <100000000>; // 100Mhz :-)
53 			timebase-frequency = <100000000>;
54 			i-cache-line-size = <32>;
55 			d-cache-line-size = <32>;
56 			i-cache-size = <32768>;
57 			d-cache-size = <32768>;
58 			dcr-controller;
59 			dcr-access-method = "native";
61 			enable-method = "spin-table";
62 			cpu-release-addr = <0 0x01f00100>;
68 			clock-frequency = <100000000>; // 100Mhz :-)
69 			timebase-frequency = <100000000>;
70 			i-cache-line-size = <32>;
71 			d-cache-line-size = <32>;
72 			i-cache-size = <32768>;
73 			d-cache-size = <32768>;
74 			dcr-controller;
75 			dcr-access-method = "native";
77 			enable-method = "spin-table";
78 			cpu-release-addr = <0 0x01f00200>;
84 			clock-frequency = <100000000>; // 100Mhz :-)
85 			timebase-frequency = <100000000>;
86 			i-cache-line-size = <32>;
87 			d-cache-line-size = <32>;
88 			i-cache-size = <32768>;
89 			d-cache-size = <32768>;
90 			dcr-controller;
91 			dcr-access-method = "native";
93 			enable-method = "spin-table";
94 			cpu-release-addr = <0 0x01f00300>;
100 		reg =  <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
104 	MPIC: interrupt-controller {
105 		compatible = "chrp,open-pic";
106 		interrupt-controller;
107 		dcr-reg = <0xffc00000 0x00030000>;
108 		#address-cells = <0>;
109 		#size-cells = <0>;
110 		#interrupt-cells = <2>;
115 		compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
116 		#address-cells = <2>;
117 		#size-cells = <1>;
119 		clock-frequency = <0>; // Filled in by zImage
122 			compatible = "ibm,opb-4xx", "ibm,opb";
123 			#address-cells = <1>;
124 			#size-cells = <1>;
125 			/* Wish there was a nicer way of specifying a full 32-bit
127 			ranges = <0x00000000 0x00000001 0x00000000 0x80000000
128 				  0x80000000 0x00000001 0x80000000 0x80000000>;
129 			clock-frequency = <0>; // Filled in by zImage
133 				reg = <0x40000200 0x00000008>;
134 				virtual-reg = <0xe0000200>;
135 				clock-frequency = <11059200>;
136 				current-speed = <115200>;
137 				interrupt-parent = <&MPIC>;
138 				interrupts = <0x0 0x2>;
144 		compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
145 		reg = <0 0xEF703000 0x2000>;
147 	iss-block {
148 		compatible = "ibm,iss-sim-block-device";
149 		reg = <0 0xEF701000 0x1000>;
153 		stdout-path = "/plb/opb/serial@40000200";