Lines Matching +full:0 +full:x020
18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
100 dcr-reg = <0x00e 0x002>;
105 dcr-reg = <0x00c 0x002>;
110 dcr-reg = <0x040 0x020>;
118 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
119 0x4 0x00200000 0x4 0x00200000 0x00000400
120 0x4 0xe0000000 0x4 0xe0000000 0x20000000
121 0xc 0x00000000 0xc 0x00000000 0x20000000
122 0xd 0x00000000 0xd 0x00000000 0x80000000
123 0xd 0x80000000 0xd 0x80000000 0x80000000
124 0xe 0x00000000 0xe 0x00000000 0x80000000
125 0xe 0x80000000 0xe 0x80000000 0x80000000
126 0xf 0x00000000 0xf 0x00000000 0x80000000
127 0xf 0x80000000 0xf 0x80000000 0x80000000>;
128 clock-frequency = <0>; /* Filled in by U-Boot */
132 dcr-reg = <0x010 0x002>;
137 dcr-reg = <0x180 0x062>;
141 interrupts = <0x0 0x1 0x2 0x3 0x4>;
143 #address-cells = <0>;
144 #size-cells = <0>;
145 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
146 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
147 /*SERR*/ 0x2 &UIC1 0x1 0x4
148 /*TXDE*/ 0x3 &UIC1 0x2 0x4
149 /*RXDE*/ 0x4 &UIC1 0x3 0x4>;
156 ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
157 clock-frequency = <0>; /* Filled in by U-Boot */
161 dcr-reg = <0x012 0x002>;
164 clock-frequency = <0>; /* Filled in by U-Boot */
166 interrupts = <0x5 0x1>;
169 nor_flash@0,0 {
172 reg = <0x00000000 0x00000000 0x01000000>;
175 partition@0 {
177 reg = <0x00000000 0x001e0000>;
181 reg = <0x001e0000 0x00020000>;
185 reg = <0x00200000 0x00200000>;
189 reg = <0x00400000 0x00b60000>;
193 reg = <0x00f60000 0x00040000>;
197 reg = <0x00fa0000 0x00060000>;
205 reg = <0xf0000200 0x00000008>;
206 virtual-reg = <0xa0000200>;
207 clock-frequency = <0>; /* Filled in by U-Boot */
210 interrupts = <0x0 0x4>;
216 reg = <0xf0000300 0x00000008>;
217 virtual-reg = <0xa0000300>;
218 clock-frequency = <0>;
219 current-speed = <0>;
221 interrupts = <0x1 0x4>;
228 reg = <0xf0000600 0x00000008>;
229 virtual-reg = <0xa0000600>;
230 clock-frequency = <0>;
231 current-speed = <0>;
233 interrupts = <0x5 0x4>;
238 reg = <0xf0000400 0x00000014>;
240 interrupts = <0x2 0x4>;
245 reg = <0xf0000500 0x00000014>;
247 interrupts = <0x3 0x4>;
249 #size-cells = <0>;
253 reg = <0x68>;
258 linux,network-index = <0x0>;
262 interrupts = <0x1c 0x4 0x1d 0x4>;
263 reg = <0xf0000800 0x00000074>;
266 mal-tx-channel = <0>;
267 mal-rx-channel = <0>;
268 cell-index = <0>;
273 phy-map = <0x00000000>;
288 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
289 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
290 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
291 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
292 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
297 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
298 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
300 /* Inbound 4GB range starting at 0 */
301 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
303 /* This drives busses 0 to 0xf */
304 bus-range = <0x0 0xf>;
307 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
308 interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
318 port = <0x0>; /* port number */
319 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
320 0x0000000c 0x10000000 0x00001000>; /* Registers */
321 dcr-reg = <0x100 0x020>;
322 sdr-base = <0x300>;
327 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
328 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
330 /* Inbound 4GB range starting at 0 */
331 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
333 /* This drives busses 0x10 to 0x1f */
334 bus-range = <0x10 0x1f>;
342 * The real slot is on idsel 0, so the swizzling is 1:1
344 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
346 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
347 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
348 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
349 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
359 port = <0x1>; /* port number */
360 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
361 0x0000000c 0x10001000 0x00001000>; /* Registers */
362 dcr-reg = <0x120 0x020>;
363 sdr-base = <0x340>;
368 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
369 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
371 /* Inbound 4GB range starting at 0 */
372 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
374 /* This drives busses 0x20 to 0x2f */
375 bus-range = <0x20 0x2f>;
383 * The real slot is on idsel 0, so the swizzling is 1:1
385 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
387 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
388 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
389 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
390 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
395 reg = <0x00000004 0x00100000 0x100>;
396 dcr-reg = <0x060 0x020>;
401 cell-index = <0>;
402 reg = <0x00000004 0x00100100 0x100>;
403 dcr-reg = <0x060 0x020>;
405 interrupts = <0 1>;
407 #address-cells = <0>;
408 #size-cells = <0>;
410 0 &UIC0 0x14 4
411 1 &UIC1 0x16 4>;
417 reg = <0x00000004 0x00100200 0x100>;
418 dcr-reg = <0x060 0x020>;
420 interrupts = <0 1>;
422 #address-cells = <0>;
423 #size-cells = <0>;
425 0 &UIC0 0x16 4
426 1 &UIC1 0x16 4>;
431 reg = <0x00000004 0x00200000 0x400>;
433 interrupts = <0x1f 4>;