Lines Matching +full:0 +full:x0a0
18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
37 i-cache-line-size = <0x20>;
38 d-cache-line-size = <0x20>;
39 i-cache-size = <0x4000>;
40 d-cache-size = <0x4000>;
48 reg = <0x00000000 0x00000000>; /* Filled in by zImage */
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
66 clock-frequency = <0>; /* Filled in by zImage */
70 dcr-reg = <0x010 0x002>;
75 dcr-reg = <0x180 0x062>;
80 0xb 0x4 /* TXEOB */
81 0xc 0x4 /* RXEOB */
82 0xa 0x4 /* SERR */
83 0xd 0x4 /* TXDE */
84 0xe 0x4 /* RXDE */>;
91 ranges = <0xef600000 0xef600000 0x00a00000>;
92 dcr-reg = <0x0a0 0x005>;
93 clock-frequency = <0>; /* Filled in by zImage */
100 reg = <0xef600400 0x00000008>;
101 virtual-reg = <0xef600400>;
102 clock-frequency = <0>; /* Filled in by zImage */
103 current-speed = <0x9600>;
105 interrupts = <0x1 0x4>;
111 reg = <0xef600300 0x00000008>;
112 virtual-reg = <0xef600300>;
113 clock-frequency = <0>; /* Filled in by zImage */
114 current-speed = <0x9600>;
116 interrupts = <0x0 0x4>;
121 #size-cells = <0>;
123 reg = <0xef600500 0x00000011>;
125 interrupts = <0x2 0x4>;
130 reg = <0x68>;
136 reg = <0x4a>;
143 reg = <0xef600700 0x00000020>;
151 gpios = <&GPIO 1 0>;
155 gpios = <&GPIO 0xe 0>;
160 linux,network-index = <0x0>;
165 0xf 0x4 /* Ethernet */
166 0x9 0x4 /* Ethernet Wake Up */>;
168 reg = <0xef600800 0x00000070>;
170 mal-tx-channel = <0>;
171 mal-rx-channel = <0>;
172 cell-index = <0>;
173 max-frame-size = <0x5dc>;
174 rx-fifo-size = <0x1000>;
175 tx-fifo-size = <0x800>;
177 phy-map = <0x00000000>;
181 linux,network-index = <0x1>;
186 0x11 0x4 /* Ethernet */
187 0x9 0x4 /* Ethernet Wake Up */>;
189 reg = <0xef600900 0x00000070>;
194 max-frame-size = <0x5dc>;
195 rx-fifo-size = <0x1000>;
196 tx-fifo-size = <0x800>;
199 phy-map = <0x0000001>;
205 dcr-reg = <0x012 0x002>;
213 clock-frequency = <0>; /* Filled in by zImage */
215 nor_flash@0 {
218 reg = <0x0 0xff800000 0x00800000>;
225 partition@0 {
227 reg = <0x7c0000 0x40000>;
232 reg = <0x400000 0x10000>;
236 reg = <0x420000 0x100000>;
240 reg = <0x520000 0x2a0000>;
244 reg = <0x410000 0x10000>;
248 reg = <0x000000 0x400000>;
252 reg = <0x7d0000 0x10000>;
264 reg = <0xeec00000 0x00000008 /* Config space access */
265 0xeed80000 0x00000004 /* IACK */
266 0xeed80000 0x00000004 /* Special cycle */
267 0xef480000 0x00000040>; /* Internal registers */
273 ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
274 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
276 /* Inbound 2GB range starting at 0 */
277 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
283 0x1800 0x0 0x0 0x1 &UIC0 0x1b 0x8
284 0x1800 0x0 0x0 0x2 &UIC0 0x1d 0x8
287 0x2000 0x0 0x0 0x1 &UIC0 0x1a 0x8
288 0x2000 0x0 0x0 0x2 &UIC0 0x1c 0x8