Lines Matching +full:0 +full:xf6000000
83 reg = <0xf 0xfe124000 0 0x2000>;
84 ranges = <0 0 0xf 0xe8000000 0x08000000
85 2 0 0xf 0xff800000 0x00010000
86 3 0 0xf 0xffdf0000 0x00008000>;
88 nor@0,0 {
92 reg = <0x0 0x0 0x8000000>;
98 nand@2,0 {
102 reg = <0x2 0x0 0x10000>;
104 partition@0 {
107 reg = <0x0 0x00100000>;
114 reg = <0x00100000 0x00100000>;
120 reg = <0x00200000 0x00A00000>;
126 reg = <0x00c00000 0x1F400000>;
131 board-control@3,0 {
135 reg = <3 0 0x300>;
136 ranges = <0 3 0 0x300>;
140 #size-cells = <0>;
143 reg = <0x54 1>;
144 mux-mask = <0xe0>;
146 t4240mdio0: mdio@0 {
148 #size-cells = <0>;
149 reg = <0>;
152 reg = <0x1>;
156 reg = <0x2>;
162 #size-cells = <0>;
163 reg = <0x20>;
166 phy1: ethernet-phy@0 {
167 reg = <0x0>;
171 reg = <0x1>;
175 reg = <0x2>;
179 reg = <0x3>;
183 reg = <0x1c>;
187 reg = <0x1d>;
191 reg = <0x1e>;
195 reg = <0x1f>;
201 #size-cells = <0>;
202 reg = <0x40>;
206 reg = <0x4>;
210 reg = <0x5>;
214 reg = <0x6>;
218 reg = <0x7>;
222 reg = <0x1c>;
226 reg = <0x1d>;
230 reg = <0x1e>;
234 reg = <0x1f>;
240 #size-cells = <0>;
241 reg = <0x60>;
245 reg = <0x8>;
249 reg = <0x9>;
253 reg = <0xa>;
257 reg = <0xb>;
261 reg = <0x1c>;
265 reg = <0x1d>;
269 reg = <0x1e>;
273 reg = <0x1f>;
279 #size-cells = <0>;
280 reg = <0x80>;
284 reg = <0xc>;
288 reg = <0xd>;
292 reg = <0xe>;
296 reg = <0xf>;
300 reg = <0x1c>;
304 reg = <0x1d>;
308 reg = <0x1e>;
312 reg = <0x1f>;
329 size = <0 0x1000000>;
330 alignment = <0 0x1000000>;
333 size = <0 0x400000>;
334 alignment = <0 0x400000>;
337 size = <0 0x2000000>;
338 alignment = <0 0x2000000>;
343 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
347 ranges = <0x0 0xf 0xf4000000 0x2000000>;
351 ranges = <0x0 0xf 0xf6000000 0x2000000>;
355 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
356 reg = <0xf 0xfe000000 0 0x00001000>;
358 flash@0 {
362 reg = <0>;
370 reg = <0x77>;
372 #size-cells = <0>;
374 i2c@0 {
376 #size-cells = <0>;
377 reg = <0>;
381 reg = <0x51>;
385 reg = <0x52>;
389 reg = <0x53>;
393 reg = <0x54>;
397 reg = <0x55>;
401 reg = <0x56>;
405 reg = <0x68>;
406 interrupts = <0x1 0x1 0 0>;
412 #size-cells = <0>;
413 reg = <0x2>;
417 reg = <0x40>;
423 reg = <0x41>;
429 reg = <0x44>;
435 reg = <0x45>;
441 reg = <0x46>;
447 reg = <0x47>;
522 xfiphy1: ethernet-phy@0 {
524 reg = <0x0>;
531 xfiphy2: ethernet-phy@0 {
533 reg = <0x0>;
598 xfiphy3: ethernet-phy@0 {
600 reg = <0x0>;
607 xfiphy4: ethernet-phy@0 {
609 reg = <0x0>;
614 xauiphy1: ethernet-phy@0 {
616 reg = <0x0>;
621 reg = <0x1>;
626 reg = <0x2>;
631 reg = <0x3>;
638 reg = <0xf 0xfe240000 0 0x10000>;
639 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
640 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
641 pcie@0 {
642 ranges = <0x02000000 0 0xe0000000
643 0x02000000 0 0xe0000000
644 0 0x20000000
646 0x01000000 0 0x00000000
647 0x01000000 0 0x00000000
648 0 0x00010000>;
653 reg = <0xf 0xfe250000 0 0x10000>;
654 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
655 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
656 pcie@0 {
657 ranges = <0x02000000 0 0xe0000000
658 0x02000000 0 0xe0000000
659 0 0x20000000
661 0x01000000 0 0x00000000
662 0x01000000 0 0x00000000
663 0 0x00010000>;
668 reg = <0xf 0xfe260000 0 0x1000>;
669 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
670 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
671 pcie@0 {
672 ranges = <0x02000000 0 0xe0000000
673 0x02000000 0 0xe0000000
674 0 0x20000000
676 0x01000000 0 0x00000000
677 0x01000000 0 0x00000000
678 0 0x00010000>;
683 reg = <0xf 0xfe270000 0 0x10000>;
684 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
685 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
686 pcie@0 {
687 ranges = <0x02000000 0 0xe0000000
688 0x02000000 0 0xe0000000
689 0 0x20000000
691 0x01000000 0 0x00000000
692 0x01000000 0 0x00000000
693 0 0x00010000>;
697 reg = <0xf 0xfe0c0000 0 0x11000>;
700 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
703 ranges = <0 0 0xc 0x30000000 0 0x10000000>;