Lines Matching +full:0 +full:xf6000000

48 			size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
67 nor@0,0 {
71 reg = <0x0 0x0 0x8000000>;
76 nand@2,0 {
80 reg = <0x2 0x0 0x10000>;
83 boardctrl: board-control@3,0 {
87 reg = <3 0 0x300>;
88 ranges = <0 3 0 0x300>;
97 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
101 ranges = <0x0 0xf 0xf4000000 0x2000000>;
105 ranges = <0x0 0xf 0xf6000000 0x2000000>;
109 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
110 reg = <0xf 0xfe000000 0 0x00001000>;
112 flash@0 {
116 reg = <0>;
140 reg = <0x77>;
142 #size-cells = <0>;
144 i2c@0 {
146 #size-cells = <0>;
147 reg = <0x0>;
151 reg = <0x50>;
156 reg = <0x51>;
161 reg = <0x57>;
166 reg = <0x68>;
167 interrupts = <0xb 0x1 0 0>;
173 #size-cells = <0>;
174 reg = <0x1>;
178 reg = <0x55>;
184 #size-cells = <0>;
185 reg = <0x2>;
189 reg = <0x40>;
195 reg = <0x41>;
202 #size-cells = <0>;
203 reg = <0x3>;
207 reg = <0x4c>;
219 reg = <0xf 0xfe240000 0 0x10000>;
220 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
221 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
222 pcie@0 {
223 ranges = <0x02000000 0 0xe0000000
224 0x02000000 0 0xe0000000
225 0 0x20000000
227 0x01000000 0 0x00000000
228 0x01000000 0 0x00000000
229 0 0x00010000>;
234 reg = <0xf 0xfe250000 0 0x10000>;
235 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
236 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
237 pcie@0 {
238 ranges = <0x02000000 0 0xe0000000
239 0x02000000 0 0xe0000000
240 0 0x20000000
242 0x01000000 0 0x00000000
243 0x01000000 0 0x00000000
244 0 0x00010000>;
249 reg = <0xf 0xfe260000 0 0x1000>;
250 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
251 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
252 pcie@0 {
253 ranges = <0x02000000 0 0xe0000000
254 0x02000000 0 0xe0000000
255 0 0x20000000
257 0x01000000 0 0x00000000
258 0x01000000 0 0x00000000
259 0 0x00010000>;
264 reg = <0xf 0xfe270000 0 0x10000>;
265 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
266 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
267 pcie@0 {
268 ranges = <0x02000000 0 0xe0000000
269 0x02000000 0 0xe0000000
270 0 0x20000000
272 0x01000000 0 0x00000000
273 0x01000000 0 0x00000000
274 0 0x00010000>;