Lines Matching +full:0 +full:x2200
39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
43 /* controller at 0xa000 */
49 bus-range = <0 255>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
54 pcie@0 {
55 reg = <0 0 0 0 0>;
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
63 /* IDSEL 0x0 */
64 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
65 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
66 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
67 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
74 interrupts = <48 2 0 0>;
78 sleep = <&pmc 0x00080000>;
99 bus-frequency = <0>; // Filled out by uboot.
101 ecm-law@0 {
103 reg = <0x0 0x1000>;
109 reg = <0x1000 0x1000>;
110 interrupts = <17 2 0 0>;
115 reg = <0x2000 0x1000>;
116 interrupts = <18 2 0 0>;
123 sleep = <&pmc 0x00000004>;
126 /include/ "pq3-i2c-0.dtsi"
135 sleep = <&pmc 0x00000002>;
138 /include/ "pq3-duart-0.dtsi"
144 reg = <0x20000 0x1000>;
146 cache-size = <0x80000>; // L2, 512K
147 interrupts = <16 2 0 0>;
150 /include/ "pq3-dma-0.dtsi"
151 /include/ "pq3-esdhc-0.dtsi"
153 sleep = <&pmc 0x00200000>;
159 reg = <0xe0100 0x100>;
160 ranges = <0x0 0xe0100 0x100>;
164 /include/ "pq3-sec3.1-0.dtsi"
166 sleep = <&pmc 0x01000000>;
170 /include/ "pq3-rmu-0.dtsi"
172 sleep = <&pmc 0x00040000>;
179 reg = <0xe0000 0x1000>;
180 ranges = <0 0xe0000 0x1000>;
186 reg = <0x70 0x20>;
196 sleep = <&pmc 0x00000800>;
197 brg-frequency = <0>;
198 bus-frequency = <0>;
205 #address-cells = <0>;
207 reg = <0x80 0x80>;
208 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
215 reg = <0x440 0x40>;
219 clock-frequency = <0>;
224 #size-cells = <0>;
226 reg = <0x4c0 0x40>;
227 cell-index = <0>;
234 #size-cells = <0>;
237 reg = <0x500 0x40>;
245 reg = <0x6c0 0x40 0x8b00 0x100>;
252 reg = <0x2000 0x200>;
259 reg = <0x2200 0x200>;
266 reg = <0x3000 0x200>;
273 reg = <0x3200 0x200>;
280 reg = <0x3400 0x200>;
287 reg = <0x3600 0x200>;
296 ranges = <0x0 0x10000 0x20000>;
298 data-only@0 {
301 reg = <0x0 0x20000>;