Lines Matching +full:brg +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <82500000>;
40 bus-frequency = <330000000>;
41 clock-frequency = <825000000>;
51 #address-cells = <1>;
52 #size-cells = <1>;
54 compatible = "simple-bus";
56 bus-frequency = <330000000>;
58 ecm-law@0 {
59 compatible = "fsl,ecm-law";
61 fsl,num-laws = <8>;
65 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
68 interrupt-parent = <&mpic>;
71 memory-controller@2000 {
72 compatible = "fsl,mpc8540-memory-controller";
74 interrupt-parent = <&mpic>;
78 L2: l2-cache-controller@20000 {
79 compatible = "fsl,mpc8540-l2-cache-controller";
81 cache-line-size = <32>; // 32 bytes
82 cache-size = <0x40000>; // L2, 256K
83 interrupt-parent = <&mpic>;
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
93 cell-index = <0>;
94 dma-channel@0 {
95 compatible = "fsl,mpc8560-dma-channel",
96 "fsl,eloplus-dma-channel";
98 cell-index = <0>;
99 interrupt-parent = <&mpic>;
102 dma-channel@80 {
103 compatible = "fsl,mpc8560-dma-channel",
104 "fsl,eloplus-dma-channel";
106 cell-index = <1>;
107 interrupt-parent = <&mpic>;
110 dma-channel@100 {
111 compatible = "fsl,mpc8560-dma-channel",
112 "fsl,eloplus-dma-channel";
114 cell-index = <2>;
115 interrupt-parent = <&mpic>;
118 dma-channel@180 {
119 compatible = "fsl,mpc8560-dma-channel",
120 "fsl,eloplus-dma-channel";
122 cell-index = <3>;
123 interrupt-parent = <&mpic>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 cell-index = <0>;
137 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupt-parent = <&mpic>;
140 tbi-handle = <&tbi0>;
141 phy-handle = <&phy0>;
144 #address-cells = <1>;
145 #size-cells = <0>;
146 compatible = "fsl,gianfar-mdio";
149 phy0: ethernet-phy@0 {
150 interrupt-parent = <&mpic>;
154 phy1: ethernet-phy@1 {
155 interrupt-parent = <&mpic>;
159 phy2: ethernet-phy@2 {
160 interrupt-parent = <&mpic>;
164 phy3: ethernet-phy@3 {
165 interrupt-parent = <&mpic>;
169 tbi0: tbi-phy@11 {
171 device_type = "tbi-phy";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 cell-index = <1>;
185 local-mac-address = [ 00 00 00 00 00 00 ];
187 interrupt-parent = <&mpic>;
188 tbi-handle = <&tbi1>;
189 phy-handle = <&phy1>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 compatible = "fsl,gianfar-tbi";
197 tbi1: tbi-phy@11 {
199 device_type = "tbi-phy";
205 interrupt-controller;
206 #address-cells = <0>;
207 #interrupt-cells = <2>;
209 compatible = "chrp,open-pic";
210 device_type = "open-pic";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
221 #address-cells = <1>;
222 #size-cells = <1>;
226 compatible = "fsl,cpm-muram-data";
231 brg@919f0 {
232 compatible = "fsl,mpc8560-brg",
233 "fsl,cpm2-brg",
234 "fsl,cpm-brg";
236 clock-frequency = <165000000>;
240 interrupt-controller;
241 #address-cells = <0>;
242 #interrupt-cells = <2>;
244 interrupt-parent = <&mpic>;
246 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
251 compatible = "fsl,mpc8560-scc-uart",
252 "fsl,cpm2-scc-uart";
254 fsl,cpm-brg = <1>;
255 fsl,cpm-command = <0x800000>;
256 current-speed = <115200>;
258 interrupt-parent = <&cpmpic>;
263 compatible = "fsl,mpc8560-scc-uart",
264 "fsl,cpm2-scc-uart";
266 fsl,cpm-brg = <2>;
267 fsl,cpm-command = <0x4a00000>;
268 current-speed = <115200>;
270 interrupt-parent = <&cpmpic>;
275 compatible = "fsl,mpc8560-fcc-enet",
276 "fsl,cpm2-fcc-enet";
278 local-mac-address = [ 00 00 00 00 00 00 ];
279 fsl,cpm-command = <0x16200300>;
281 interrupt-parent = <&cpmpic>;
282 phy-handle = <&phy2>;
287 compatible = "fsl,mpc8560-fcc-enet",
288 "fsl,cpm2-fcc-enet";
290 local-mac-address = [ 00 00 00 00 00 00 ];
291 fsl,cpm-command = <0x1a400300>;
293 interrupt-parent = <&cpmpic>;
294 phy-handle = <&phy3>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
306 clock-frequency = <66666666>;
307 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
308 interrupt-map = <
382 interrupt-parent = <&mpic>;
384 bus-range = <0 0>;