Lines Matching +full:brg +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 bus-frequency = <0>; // 166 MHz
40 clock-frequency = <0>; // 825 MHz, from uboot
41 next-level-cache = <&L2>;
51 #address-cells = <1>;
52 #size-cells = <1>;
54 compatible = "simple-bus";
56 bus-frequency = <0>;
58 ecm-law@0 {
59 compatible = "fsl,ecm-law";
61 fsl,num-laws = <8>;
65 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
68 interrupt-parent = <&mpic>;
71 memory-controller@2000 {
72 compatible = "fsl,mpc8555-memory-controller";
74 interrupt-parent = <&mpic>;
78 L2: l2-cache-controller@20000 {
79 compatible = "fsl,mpc8555-l2-cache-controller";
81 cache-line-size = <32>; // 32 bytes
82 cache-size = <0x40000>; // L2, 256K
83 interrupt-parent = <&mpic>;
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cell-index = <0>;
91 compatible = "fsl-i2c";
94 interrupt-parent = <&mpic>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
104 cell-index = <0>;
105 dma-channel@0 {
106 compatible = "fsl,mpc8555-dma-channel",
107 "fsl,eloplus-dma-channel";
109 cell-index = <0>;
110 interrupt-parent = <&mpic>;
113 dma-channel@80 {
114 compatible = "fsl,mpc8555-dma-channel",
115 "fsl,eloplus-dma-channel";
117 cell-index = <1>;
118 interrupt-parent = <&mpic>;
121 dma-channel@100 {
122 compatible = "fsl,mpc8555-dma-channel",
123 "fsl,eloplus-dma-channel";
125 cell-index = <2>;
126 interrupt-parent = <&mpic>;
129 dma-channel@180 {
130 compatible = "fsl,mpc8555-dma-channel",
131 "fsl,eloplus-dma-channel";
133 cell-index = <3>;
134 interrupt-parent = <&mpic>;
140 #address-cells = <1>;
141 #size-cells = <1>;
142 cell-index = <0>;
148 local-mac-address = [ 00 00 00 00 00 00 ];
150 interrupt-parent = <&mpic>;
151 tbi-handle = <&tbi0>;
152 phy-handle = <&phy0>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,gianfar-mdio";
160 phy0: ethernet-phy@0 {
161 interrupt-parent = <&mpic>;
165 phy1: ethernet-phy@1 {
166 interrupt-parent = <&mpic>;
170 tbi0: tbi-phy@11 {
172 device_type = "tbi-phy";
178 #address-cells = <1>;
179 #size-cells = <1>;
180 cell-index = <1>;
186 local-mac-address = [ 00 00 00 00 00 00 ];
188 interrupt-parent = <&mpic>;
189 tbi-handle = <&tbi1>;
190 phy-handle = <&phy1>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,gianfar-tbi";
198 tbi1: tbi-phy@11 {
200 device_type = "tbi-phy";
206 cell-index = <0>;
210 clock-frequency = <0>; // should we fill in in uboot?
212 interrupt-parent = <&mpic>;
216 cell-index = <1>;
220 clock-frequency = <0>; // should we fill in in uboot?
222 interrupt-parent = <&mpic>;
229 interrupt-parent = <&mpic>;
230 fsl,num-channels = <4>;
231 fsl,channel-fifo-len = <24>;
232 fsl,exec-units-mask = <0x7e>;
233 fsl,descriptor-types-mask = <0x01010ebf>;
237 interrupt-controller;
238 #address-cells = <0>;
239 #interrupt-cells = <2>;
241 compatible = "chrp,open-pic";
242 device_type = "open-pic";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
253 #address-cells = <1>;
254 #size-cells = <1>;
258 compatible = "fsl,cpm-muram-data";
263 brg@919f0 {
264 compatible = "fsl,mpc8555-brg",
265 "fsl,cpm2-brg",
266 "fsl,cpm-brg";
271 interrupt-controller;
272 #address-cells = <0>;
273 #interrupt-cells = <2>;
275 interrupt-parent = <&mpic>;
277 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
283 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
284 interrupt-map = <
328 interrupt-parent = <&mpic>;
330 bus-range = <0 0>;
333 clock-frequency = <66666666>;
334 #interrupt-cells = <1>;
335 #size-cells = <2>;
336 #address-cells = <3>;
338 compatible = "fsl,mpc8540-pci";
342 interrupt-controller;
343 device_type = "interrupt-controller";
345 #address-cells = <0>;
346 #interrupt-cells = <2>;
349 interrupt-parent = <&pci0>;
354 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
355 interrupt-map = <
362 interrupt-parent = <&mpic>;
364 bus-range = <0 0>;
367 clock-frequency = <66666666>;
368 #interrupt-cells = <1>;
369 #size-cells = <2>;
370 #address-cells = <3>;
372 compatible = "fsl,mpc8540-pci";