Lines Matching +full:0 +full:xffe00000

17 		#size-cells = <0>;
19 		PowerPC,8536@0 {
21 			reg = <0>;
28 		reg = <0 0 0 0>;	// Filled by U-Boot
32 		reg = <0 0xffe05000 0 0x1000>;
34 		ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
35 			  0x2 0x0 0x0 0xffa00000 0x00040000
36 			  0x3 0x0 0x0 0xffdf0000 0x00008000>;
40 		ranges = <0x0 0 0xffe00000 0x100000>;
44 		reg = <0 0xffe08000 0 0x1000>;
45 		ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
46 			  0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
48 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
51 			/* IDSEL 0x11 J17 Slot 1 */
52 			0x8800 0 0 1 &mpic 1 1 0 0
53 			0x8800 0 0 2 &mpic 2 1 0 0
54 			0x8800 0 0 3 &mpic 3 1 0 0
55 			0x8800 0 0 4 &mpic 4 1 0 0>;
59 		reg = <0 0xffe09000 0 0x1000>;
60 		ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
61 			  0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
62 		pcie@0 {
63 			ranges = <0x02000000 0 0x98000000
64 				  0x02000000 0 0x98000000
65 				  0 0x08000000
67 				  0x01000000 0 0x00000000
68 				  0x01000000 0 0x00000000
69 				  0 0x00010000>;
74 		reg = <0 0xffe0a000 0 0x1000>;
75 		ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
76 			  0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
77 		pcie@0 {
78 			ranges = <0x02000000 0 0x90000000
79 				  0x02000000 0 0x90000000
80 				  0 0x08000000
82 				  0x01000000 0 0x00000000
83 				  0x01000000 0 0x00000000
84 				  0 0x00010000>;
89 		reg = <0 0xffe0b000 0 0x1000>;
90 		ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
91 			  0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
92 		pcie@0 {
93 			ranges = <0x02000000 0 0xa0000000
94 				  0x02000000 0 0xa0000000
95 				  0 0x20000000
97 				  0x01000000 0 0x00000000
98 				  0x01000000 0 0x00000000
99 				  0 0x00100000>;