Lines Matching +full:0 +full:xfb000000
30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
57 reg = <0xf 0xfe000000 0 0x00001000>;
59 flash@0 {
63 reg = <0>;
120 reg = <0x11>;
153 reg = <0xf 0xfe124000 0 0x1000>;
154 ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
155 1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
156 2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
157 3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
159 nand@0,0 {
163 reg = <0 0 0x40000>;
166 board-control@1,0 {
168 reg = <1 0 0x80>;
171 chassis-mgmt@3,0 {
175 reg = <3 0 0x100>;
177 interrupts = <6 1 0 0>;
182 reg = <0xf 0xfe200000 0 0x1000>;
183 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
184 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
185 pcie@0 {
186 ranges = <0x02000000 0 0xe0000000
187 0x02000000 0 0xe0000000
188 0 0x20000000
190 0x01000000 0 0x00000000
191 0x01000000 0 0x00000000
192 0 0x00010000>;
201 reg = <0xf 0xfe202000 0 0x1000>;
202 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
203 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
204 pcie@0 {
205 ranges = <0x02000000 0 0xe0000000
206 0x02000000 0 0xe0000000
207 0 0x20000000
209 0x01000000 0 0x00000000
210 0x01000000 0 0x00000000
211 0 0x00010000>;