Lines Matching +full:0 +full:x020
18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
100 dcr-reg = <0x00e 0x002>;
105 dcr-reg = <0x00c 0x002>;
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
114 standby = <0xfeff791d>;
119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
120 0x030 0x008>; /* L2 cache DCR's */
132 clock-frequency = <0>; /* Filled in by U-Boot */
136 dcr-reg = <0x010 0x002>;
141 reg = <4 0x00180000 0x80400>;
143 interrupts = <0x1d 0x4>;
148 reg = <4 0x00110000 0x50>;
153 dcr-reg = <0x180 0x062>;
156 #address-cells = <0>;
157 #size-cells = <0>;
159 interrupts = < /*TXEOB*/ 0x6 0x4
160 /*RXEOB*/ 0x7 0x4
161 /*SERR*/ 0x3 0x4
162 /*TXDE*/ 0x4 0x4
163 /*RXDE*/ 0x5 0x4>;
169 interrupts = <0x1d 4>;
170 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
175 reg = <4 0xbffd0000 0x60>;
177 interrupts = <0x1e 4>;
182 reg = <0x4 0xbff80000 0x10000>;
185 #address-cells = <0>;
186 #size-cells = <0>;
187 interrupts = <0x0 0x1 0x2>;
188 interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
189 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
190 /* DMA */ 0x2 &UIC0 0xc 0x4>;
195 reg = <4 0xbffd0800 0x400>;
197 interrupts = <0x5 0x4>;
203 reg = <4 0xbffd1000 0x800>;
205 interrupts = <0x0 0x4>;
206 dmas = <&AHBDMA 0 1 0>;
214 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
215 clock-frequency = <0>; /* Filled in by U-Boot */
219 dcr-reg = <0x012 0x002>;
222 clock-frequency = <0>; /* Filled in by U-Boot */
224 interrupts = <0x6 0x4>;
227 nor_flash@0,0 {
230 reg = <0x00000000 0x00000000 0x04000000>;
233 partition@0 {
235 reg = <0x00000000 0x001e0000>;
239 reg = <0x001e0000 0x00020000>;
243 reg = <0x00200000 0x01400000>;
247 reg = <0x01600000 0x00400000>;
251 reg = <0x01a00000 0x02560000>;
255 reg = <0x03f60000 0x00040000>;
259 reg = <0x03fa0000 0x00060000>;
263 cpld@2,0 {
265 reg = <2 0x0 0x9>;
268 ndfc@3,0 {
270 reg = <0x00000003 0x00000000 0x00002000>;
271 ccr = <0x00001000>;
272 bank-settings = <0x80002222>;
280 partition@0 {
282 reg = <0x00000000 0x00100000>;
286 reg = <0x00000000 0x03f00000>;
295 reg = <0xef600300 0x00000008>;
296 virtual-reg = <0xef600300>;
297 clock-frequency = <0>; /* Filled in by U-Boot */
298 current-speed = <0>; /* Filled in by U-Boot */
300 interrupts = <0x1 0x4>;
306 reg = <0xef600400 0x00000008>;
307 virtual-reg = <0xef600400>;
308 clock-frequency = <0>; /* Filled in by U-Boot */
309 current-speed = <0>; /* Filled in by U-Boot */
311 interrupts = <0x1 0x4>;
316 reg = <0xef600700 0x00000014>;
318 interrupts = <0x2 0x4>;
320 #size-cells = <0>;
323 reg = <0x68>;
325 interrupts = <0x19 0x8>;
329 reg = <0x48>;
331 interrupts = <0x14 0x8>;
337 reg = <0xef600800 0x00000014>;
339 interrupts = <0x3 0x4>;
344 reg = <0xef600b00 0x00000048>;
350 reg = <0xef600d00 0x0000000c>;
355 reg = <0xef601500 0x00000008>;
361 reg = <0xef601350 0x00000030>;
366 reg = <0xef601450 0x00000030>;
373 interrupts = <0x0 0x1>;
375 #address-cells = <0>;
376 #size-cells = <0>;
377 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
378 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
379 reg = <0xef600e00 0x000000c4>;
382 mal-tx-channel = <0>;
383 mal-rx-channel = <0>;
384 cell-index = <0>;
390 phy-map = <0x00000000>;
392 rgmii-channel = <0>;
394 tah-channel = <0>;
403 interrupts = <0x0 0x1>;
405 #address-cells = <0>;
406 #size-cells = <0>;
407 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
408 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
409 reg = <0xef600f00 0x000000c4>;
420 phy-map = <0x00000000>;
440 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
441 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
442 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
443 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
444 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
449 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
450 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
451 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
453 /* Inbound 2GB range starting at 0 */
454 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
456 /* This drives busses 0 to 0x3f */
457 bus-range = <0x0 0x3f>;
459 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
460 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
461 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
471 port = <0x0>; /* port number */
472 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
473 0x0000000c 0x08010000 0x00001000>; /* Registers */
474 dcr-reg = <0x100 0x020>;
475 sdr-base = <0x300>;
480 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
481 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
482 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
484 /* Inbound 2GB range starting at 0 */
485 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
487 /* This drives busses 40 to 0x7f */
488 bus-range = <0x40 0x7f>;
496 * The real slot is on idsel 0, so the swizzling is 1:1
498 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
500 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
501 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
502 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
503 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
513 port = <0x1>; /* port number */
514 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
515 0x0000000c 0x08011000 0x00001000>; /* Registers */
516 dcr-reg = <0x120 0x020>;
517 sdr-base = <0x340>;
522 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
523 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
524 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
526 /* Inbound 2GB range starting at 0 */
527 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
529 /* This drives busses 80 to 0xbf */
530 bus-range = <0x80 0xbf>;
538 * The real slot is on idsel 0, so the swizzling is 1:1
540 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
542 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
543 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
544 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
545 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;