Lines Matching +full:0 +full:x008
24 dcr-parent = <&{/cpus/cpu@0}>;
35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x00000000>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
55 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
61 cell-index = <0>;
62 dcr-reg = <0x0c0 0x009>;
63 #address-cells = <0>;
64 #size-cells = <0>;
72 dcr-reg = <0x0d0 0x009>;
73 #address-cells = <0>;
74 #size-cells = <0>;
76 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
84 dcr-reg = <0x0e0 0x009>;
85 #address-cells = <0>;
86 #size-cells = <0>;
88 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
96 dcr-reg = <0x0f0 0x009>;
97 #address-cells = <0>;
98 #size-cells = <0>;
100 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
106 dcr-reg = <0x00e 0x002>;
111 dcr-reg = <0x00c 0x002>;
116 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
117 0x030 0x008>; /* L2 cache DCR's */
129 clock-frequency = <0>; /* Filled in by U-Boot */
133 dcr-reg = <0x010 0x002>;
138 reg = <4 0x00180000 0x80400>;
140 interrupts = <0x1d 0x4>;
145 dcr-reg = <0x180 0x062>;
148 #address-cells = <0>;
149 #size-cells = <0>;
151 interrupts = < /*TXEOB*/ 0x6 0x4
152 /*RXEOB*/ 0x7 0x4
153 /*SERR*/ 0x3 0x4
154 /*TXDE*/ 0x4 0x4
155 /*RXDE*/ 0x5 0x4>;
156 desc-base-addr-high = <0x8>;
163 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
164 clock-frequency = <0>; /* Filled in by U-Boot */
168 dcr-reg = <0x012 0x002>;
171 clock-frequency = <0>; /* Filled in by U-Boot */
173 interrupts = <0x6 0x4>;
176 nor_flash@0,0 {
179 reg = <0x00000000 0x00000000 0x02000000>;
182 partition@0 {
184 reg = <0x00000000 0x001e0000>;
188 reg = <0x001e0000 0x00020000>;
192 reg = <0x00200000 0x00200000>;
196 reg = <0x00400000 0x01b60000>;
200 reg = <0x01f60000 0x00040000>;
204 reg = <0x01fa0000 0x00060000>;
212 reg = <0xef600300 0x00000008>;
213 virtual-reg = <0xef600300>;
214 clock-frequency = <0>; /* Filled in by U-Boot */
215 current-speed = <0>; /* Filled in by U-Boot */
217 interrupts = <0x1 0x4>;
222 reg = <0xef600700 0x00000014>;
224 interrupts = <0x2 0x4>;
226 #size-cells = <0>;
229 reg = <0x4a>;
231 interrupts = <0x0 0x8>;
237 reg = <0xef600800 0x00000014>;
239 interrupts = <0x3 0x4>;
244 reg = <0xef601350 0x00000030>;
249 reg = <0xef601450 0x00000030>;
256 interrupts = <0x0 0x1>;
258 #address-cells = <0>;
259 #size-cells = <0>;
260 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
261 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
262 reg = <0xef600e00 0x000000c4>;
265 mal-tx-channel = <0>;
266 mal-rx-channel = <0>;
267 cell-index = <0>;
273 phy-map = <0xffffffff>;
274 gpcs-address = <0x0000000a>;
276 tah-channel = <0>;
285 interrupts = <0x0 0x1>;
287 #address-cells = <0>;
288 #size-cells = <0>;
289 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
290 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
291 reg = <0xef600f00 0x000000c4>;
302 phy-map = <0x00000000>;
303 gpcs-address = <0x0000000b>;
315 interrupts = <0x0 0x1>;
317 #address-cells = <0>;
318 #size-cells = <0>;
319 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
320 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
321 reg = <0xef601100 0x000000c4>;
333 phy-map = <0x00000001>;
334 gpcs-address = <0x0000000C>;