Lines Matching +full:0 +full:x4c00000
27 reg = <0x0 0x10000000
28 0x30000000 0x30000000>;
45 led-0 {
65 gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
70 eth0_power: fixedregulator-0 {
77 gpio = <&gpb 25 0>;
110 gpio = <&gpb 19 0>;
121 gpio = <&gpf 15 0>;
172 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
176 assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>;
182 * use channel #0 and #1 for the per cpu system timers,
200 pinctrl-0 = <&pins_mmc0>;
218 pinctrl-0 = <&pins_mmc1>;
221 #size-cells = <0>;
237 pinctrl-0 = <&pins_uart0>;
244 pinctrl-0 = <&pins_uart1>;
251 pinctrl-0 = <&pins_uart2>;
277 pinctrl-0 = <&pins_uart3>;
284 pinctrl-0 = <&pins_uart4>;
291 pinctrl-0 = <&pins_i2c0>;
297 reg = <0x5a>;
371 pinctrl-0 = <&pins_i2c1>;
379 pinctrl-0 = <&pins_i2c2>;
387 pinctrl-0 = <&pins_i2c3>;
395 pinctrl-0 = <&pins_i2c4>;
401 reg = <0x51>;
413 reg = <1 0 0x1000000>;
416 #size-cells = <0>;
431 pinctrl-0 = <&pins_nemc>;
442 pinctrl-0 = <&pins_nemc_cs1>;
449 partition@0 {
451 reg = <0x0 0x0 0x0 0x800000>;
456 reg = <0x0 0x800000 0x0 0x200000>;
461 reg = <0x0 0xa00000 0x0 0x200000>;
466 reg = <0x0 0xc00000 0x0 0x4000000>;
471 reg = <0x0 0x4c00000 0x1 0xfb400000>;
482 pinctrl-0 = <&pins_nemc_cs6>;
484 reg = <6 0 1>, /* addr */
620 pinctrl-0 = <&pins_hdmi_ddc>;
624 #size-cells = <0>;
626 port@0 {
627 reg = <0>;