Lines Matching +full:0 +full:x17fff000

24 		#size-cells = <0>;
26 		cpu@0 {
29 			reg = <0>;
34 	memory@0 {
36 		reg = <0x00000000 0x10000000>;
42 		reg = <0x10000000 0x2000000>;
51 		ranges = <0x02000000 0 0x40000000
52 			  0x40000000 0 0x40000000>;
54 		bus-range = <0x00 0xff>;
56 		interrupt-map-mask = <0 0 0 7>;
57 		interrupt-map = <0 0 0 1 &pci0_intc 1>,
58 				<0 0 0 2 &pci0_intc 2>,
59 				<0 0 0 3 &pci0_intc 3>,
60 				<0 0 0 4 &pci0_intc 4>;
64 			#address-cells = <0>;
72 		reg = <0x12000000 0x2000000>;
81 		ranges = <0x02000000 0 0x20000000
82 			  0x20000000 0 0x20000000>;
84 		bus-range = <0x00 0xff>;
86 		interrupt-map-mask = <0 0 0 7>;
87 		interrupt-map = <0 0 0 1 &pci1_intc 1>,
88 				<0 0 0 2 &pci1_intc 2>,
89 				<0 0 0 3 &pci1_intc 3>,
90 				<0 0 0 4 &pci1_intc 4>;
94 			#address-cells = <0>;
102 		reg = <0x14000000 0x2000000>;
109 		interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
111 		ranges = <0x02000000 0 0x16000000
112 			  0x16000000 0 0x100000>;
114 		bus-range = <0x00 0xff>;
116 		interrupt-map-mask = <0 0 0 7>;
117 		interrupt-map = <0 0 0 1 &pci2_intc 1>,
118 				<0 0 0 2 &pci2_intc 2>,
119 				<0 0 0 3 &pci2_intc 3>,
120 				<0 0 0 4 &pci2_intc 4>;
124 			#address-cells = <0>;
128 		pci2_root@0,0 {
130 			reg = <0x00000000 0 0 0 0>;
136 			eg20t_bridge@1,0,0 {
138 				reg = <0x00010000 0 0 0 0>;
144 				eg20t_phub@2,0,0 {
146 					reg = <0x00020000 0 0 0 0>;
147 					intel,eg20t-prefetch = <0>;
150 				eg20t_mac@2,0,1 {
152 					reg = <0x00020100 0 0 0 0>;
157 				eg20t_gpio: eg20t_gpio@2,0,2 {
159 					reg = <0x00020200 0 0 0 0>;
167 					reg = <0x00026200 0 0 0 0>;
170 					#size-cells = <0>;
174 						reg = <0x68>;
183 		reg = <0x16120000 0x20000>;
197 		reg = <0x16140000 0x8000>;
202 		reg = <0x16200000 0x8000>;
207 		reg = <0x17ffd000 0x1000>;
218 		offset = <0x10>;
219 		mask = <0x10>;
224 		reg = <0x17ffe000 0x1000>;
235 		reg = <0x17fff000 0x8>;