Lines Matching +full:0 +full:x4105
13 soc@0 {
15 phy0: ethernet-phy@0 {
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
43 <3 0x11 0 0x00aa>,
44 <3 0x12 0 0x4105>,
45 <3 0x13 0 0x0a60>;
50 marvell,reg-init = <3 0x10 0 0x5777>,
51 <3 0x11 0 0x00aa>,
52 <3 0x12 0 0x4105>,
53 <3 0x13 0 0x0a60>;
58 marvell,reg-init = <3 0x10 0 0x5777>,
59 <3 0x11 0 0x00aa>,
60 <3 0x12 0 0x4105>,
61 <3 0x13 0 0x0a60>;
66 marvell,reg-init = <3 0x10 0 0x5777>,
67 <3 0x11 0 0x00aa>,
68 <3 0x12 0 0x4105>,
69 <3 0x13 0 0x0a60>;
75 marvell,reg-init = <3 0x10 0 0x5777>,
76 <3 0x11 0 0x00aa>,
77 <3 0x12 0 0x4105>,
78 <3 0x13 0 0x0a60>;
83 marvell,reg-init = <3 0x10 0 0x5777>,
84 <3 0x11 0 0x00aa>,
85 <3 0x12 0 0x4105>,
86 <3 0x13 0 0x0a60>;
91 marvell,reg-init = <3 0x10 0 0x5777>,
92 <3 0x11 0 0x00aa>,
93 <3 0x12 0 0x4105>,
94 <3 0x13 0 0x0a60>;
99 marvell,reg-init = <3 0x10 0 0x5777>,
100 <3 0x11 0 0x00aa>,
101 <3 0x12 0 0x4105>,
102 <3 0x13 0 0x0a60>;
109 #size-cells = <0>;
110 reg = <0x11800 0x00001900 0x0 0x40>;
115 marvell,reg-init = <3 0x10 0 0x5777>,
116 <3 0x11 0 0x00aa>,
117 <3 0x12 0 0x4105>,
118 <3 0x13 0 0x0a60>;
125 marvell,reg-init = <3 0x10 0 0x5777>,
126 <3 0x11 0 0x00aa>,
127 <3 0x12 0 0x4105>,
128 <3 0x13 0 0x0a60>;
135 marvell,reg-init = <3 0x10 0 0x5777>,
136 <3 0x11 0 0x00aa>,
137 <3 0x12 0 0x4105>,
138 <3 0x13 0 0x0a60>;
145 marvell,reg-init = <3 0x10 0 0x5777>,
146 <3 0x11 0 0x00aa>,
147 <3 0x12 0 0x4105>,
148 <3 0x13 0 0x0a60>;
156 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
157 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
158 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
159 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
160 cell-index = <0>;
161 interrupts = <0 62>, <1 46>;
168 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
169 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
170 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
171 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
179 interface@0 {
180 ethernet@0 {
183 rx-delay = <0>;
184 tx-delay = <0>;
193 rx-delay = <0>;
194 tx-delay = <0>;
203 rx-delay = <0>;
204 tx-delay = <0>;
208 reg = <0x3>; /* Port */
215 reg = <0x4>; /* Port */
220 reg = <0x5>; /* Port */
225 reg = <0x6>; /* Port */
230 reg = <0x7>; /* Port */
235 reg = <0x8>; /* Port */
240 reg = <0x9>; /* Port */
245 reg = <0xa>; /* Port */
250 reg = <0xb>; /* Port */
255 reg = <0xc>; /* Port */
260 reg = <0xd>; /* Port */
265 reg = <0xe>; /* Port */
270 reg = <0xf>; /* Port */
276 ethernet@0 {
278 reg = <0x0>; /* Port */
284 reg = <0x1>; /* Port */
290 reg = <0x2>; /* Port */
296 reg = <0x3>; /* Port */
306 reg = <0x68>;
310 reg = <0x4c>;
316 #size-cells = <0>;
318 reg = <0x11800 0x00001200 0x0 0x200>;
319 interrupts = <0 59>;
325 reg = <0x11800 0x00000c00 0x0 0x400>;
326 clock-frequency = <0>;
329 interrupts = <0 35>;
334 reg = <0x11800 0x00000400 0x0 0x400>;
335 clock-frequency = <0>;
342 led0: led-display@4,0 {
344 reg = <4 0x20 0x20>, <4 0 0x20>;
347 cf0: compact-flash@5,0 {
349 reg = <5 0 0x10000>, <6 0 0x10000>;
358 reg = <0x11800 0x6f000000 0x0 0x100>;
369 reg = <0x16f00 0x00000000 0x0 0x100>;
370 interrupts = <0 56>;
375 reg = <0x16f00 0x00000400 0x0 0x100>;
376 interrupts = <0 56>;