Lines Matching +full:sata3 +full:- +full:ahci
1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <81000000>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <27000000>;
53 #address-cells = <1>;
54 #size-cells = <1>;
56 compatible = "simple-bus";
59 periph_intc: interrupt-controller@411400 {
60 compatible = "brcm,bcm7038-l1-intc";
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
71 compatible = "brcm,l2-intc";
73 interrupt-controller;
74 #interrupt-cells = <1>;
75 interrupt-parent = <&periph_intc>;
79 gisb-arb@400000 {
80 compatible = "brcm,bcm7400-gisb-arb";
82 native-endian;
83 interrupt-parent = <&sun_l2_intc>;
85 brcm,gisb-arb-master-mask = <0x2f3>;
86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
91 upg_irq0_intc: interrupt-controller@406600 {
92 compatible = "brcm,bcm7120-l2-intc";
95 brcm,int-map-mask = <0x44>, <0x7000000>;
96 brcm,int-fwd-mask = <0x70000>;
98 interrupt-controller;
99 #interrupt-cells = <1>;
101 interrupt-parent = <&periph_intc>;
103 interrupt-names = "upg_main", "upg_bsc";
106 upg_aon_irq0_intc: interrupt-controller@408b80 {
107 compatible = "brcm,bcm7120-l2-intc";
110 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
111 brcm,int-fwd-mask = <0>;
112 brcm,irq-can-wake;
114 interrupt-controller;
115 #interrupt-cells = <1>;
117 interrupt-parent = <&periph_intc>;
119 interrupt-names = "upg_main_aon", "upg_bsc_aon",
124 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
126 native-endian;
130 compatible = "brcm,brcmstb-reboot";
137 reg-io-width = <0x4>;
138 reg-shift = <0x2>;
139 native-endian;
140 interrupt-parent = <&periph_intc>;
149 reg-io-width = <0x4>;
150 reg-shift = <0x2>;
151 native-endian;
152 interrupt-parent = <&periph_intc>;
161 reg-io-width = <0x4>;
162 reg-shift = <0x2>;
163 native-endian;
164 interrupt-parent = <&periph_intc>;
171 clock-frequency = <390000>;
172 compatible = "brcm,brcmstb-i2c";
173 interrupt-parent = <&upg_irq0_intc>;
176 interrupt-names = "upg_bsca";
181 clock-frequency = <390000>;
182 compatible = "brcm,brcmstb-i2c";
183 interrupt-parent = <&upg_irq0_intc>;
186 interrupt-names = "upg_bscb";
191 clock-frequency = <390000>;
192 compatible = "brcm,brcmstb-i2c";
193 interrupt-parent = <&upg_aon_irq0_intc>;
196 interrupt-names = "upg_bscd";
201 compatible = "brcm,bcm7038-pwm";
203 #pwm-cells = <2>;
210 compatible = "brcm,bcm7038-wdt";
215 aon_pm_l2_intc: interrupt-controller@408440 {
216 compatible = "brcm,l2-intc";
218 interrupt-controller;
219 #interrupt-cells = <1>;
220 interrupt-parent = <&periph_intc>;
222 brcm,irq-can-wake;
226 compatible = "brcm,brcmstb-aon-ctrl";
228 reg-names = "aon-ctrl", "aon-sram";
232 compatible = "brcm,brcmstb-timers";
237 compatible = "brcm,brcmstb-gpio";
239 #gpio-cells = <2>;
240 #interrupt-cells = <2>;
241 gpio-controller;
242 interrupt-controller;
243 interrupt-parent = <&upg_irq0_intc>;
245 brcm,gpio-bank-widths = <32 32 32 29 4>;
249 compatible = "brcm,brcmstb-gpio";
251 #gpio-cells = <2>;
252 #interrupt-cells = <2>;
253 gpio-controller;
254 interrupt-controller;
255 interrupt-parent = <&upg_aon_irq0_intc>;
257 interrupts-extended = <&upg_aon_irq0_intc 6>,
259 wakeup-source;
260 brcm,gpio-bank-widths = <21 32 2>;
264 phy-mode = "internal";
265 phy-handle = <&phy1>;
266 mac-address = [ 00 10 18 36 23 1a ];
267 compatible = "brcm,genet-v2";
268 #address-cells = <0x1>;
269 #size-cells = <0x1>;
272 interrupt-parent = <&periph_intc>;
276 compatible = "brcm,genet-mdio-v2";
277 #address-cells = <0x1>;
278 #size-cells = <0x0>;
281 phy1: ethernet-phy@1 {
282 max-speed = <100>;
284 compatible = "brcm,40nm-ephy",
285 "ethernet-phy-ieee802.3-c22";
291 compatible = "brcm,bcm7362-ehci", "generic-ehci";
293 native-endian;
294 interrupt-parent = <&periph_intc>;
300 compatible = "brcm,bcm7362-ohci", "generic-ohci";
302 native-endian;
303 no-big-frame-no;
304 interrupt-parent = <&periph_intc>;
309 hif_l2_intc: interrupt-controller@411000 {
310 compatible = "brcm,l2-intc";
312 interrupt-controller;
313 #interrupt-cells = <1>;
314 interrupt-parent = <&periph_intc>;
319 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 reg-names = "nand";
324 interrupt-parent = <&hif_l2_intc>;
330 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
331 reg-names = "ahci", "top-ctrl";
333 interrupt-parent = <&periph_intc>;
335 #address-cells = <1>;
336 #size-cells = <0>;
339 sata0: sata-port@0 {
344 sata1: sata-port@1 {
350 sata_phy: sata-phy@180100 {
351 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
353 reg-names = "phy";
354 #address-cells = <1>;
355 #size-cells = <0>;
358 sata_phy0: sata-phy@0 {
360 #phy-cells = <0>;
363 sata_phy1: sata-phy@1 {
365 #phy-cells = <0>;
370 compatible = "brcm,bcm7425-sdhci";
372 interrupt-parent = <&periph_intc>;
377 spi_l2_intc: interrupt-controller@411d00 {
378 compatible = "brcm,l2-intc";
380 interrupt-controller;
381 #interrupt-cells = <1>;
382 interrupt-parent = <&periph_intc>;
387 #address-cells = <0x1>;
388 #size-cells = <0x0>;
389 compatible = "brcm,spi-bcm-qspi",
390 "brcm,spi-brcmstb-qspi";
393 reg-names = "cs_reg", "hif_mspi", "bspi";
395 interrupt-parent = <&spi_l2_intc>;
396 interrupt-names = "spi_lr_fullness_reached",
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "brcm,spi-bcm-qspi",
410 "brcm,spi-brcmstb-mspi";
413 reg-names = "mspi";
415 interrupt-parent = <&upg_aon_irq0_intc>;
416 interrupt-names = "mspi_done";
421 compatible = "brcm,brcmstb-waketimer";
424 interrupt-parent = <&aon_pm_l2_intc>;
425 interrupt-names = "timer";
432 compatible = "simple-bus";
434 #address-cells = <1>;
435 #size-cells = <1>;
437 memory-controller@0 {
438 compatible = "brcm,brcmstb-memc", "simple-bus";
440 #address-cells = <1>;
441 #size-cells = <1>;
443 memc-arb@1000 {
444 compatible = "brcm,brcmstb-memc-arb";
448 memc-ddr@2000 {
449 compatible = "brcm,brcmstb-memc-ddr";
453 ddr-phy@6000 {
454 compatible = "brcm,brcmstb-ddr-phy";
459 compatible = "brcm,brcmstb-ddr-shimphy";