Lines Matching +full:phy +full:- +full:sata3
1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <81000000>;
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <27000000>;
47 #address-cells = <1>;
48 #size-cells = <1>;
50 compatible = "simple-bus";
53 periph_intc: interrupt-controller@411400 {
54 compatible = "brcm,bcm7038-l1-intc";
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
65 compatible = "brcm,l2-intc";
67 interrupt-controller;
68 #interrupt-cells = <1>;
69 interrupt-parent = <&periph_intc>;
73 gisb-arb@400000 {
74 compatible = "brcm,bcm7400-gisb-arb";
76 native-endian;
77 interrupt-parent = <&sun_l2_intc>;
79 brcm,gisb-arb-master-mask = <0x2f3>;
80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
85 upg_irq0_intc: interrupt-controller@406600 {
86 compatible = "brcm,bcm7120-l2-intc";
89 brcm,int-map-mask = <0x44>, <0x7000000>;
90 brcm,int-fwd-mask = <0x70000>;
92 interrupt-controller;
93 #interrupt-cells = <1>;
95 interrupt-parent = <&periph_intc>;
97 interrupt-names = "upg_main", "upg_bsc";
100 upg_aon_irq0_intc: interrupt-controller@408b80 {
101 compatible = "brcm,bcm7120-l2-intc";
104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
105 brcm,int-fwd-mask = <0>;
106 brcm,irq-can-wake;
108 interrupt-controller;
109 #interrupt-cells = <1>;
111 interrupt-parent = <&periph_intc>;
113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
118 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
120 native-endian;
124 compatible = "brcm,brcmstb-reboot";
131 reg-io-width = <0x4>;
132 reg-shift = <0x2>;
133 native-endian;
134 interrupt-parent = <&periph_intc>;
143 reg-io-width = <0x4>;
144 reg-shift = <0x2>;
145 native-endian;
146 interrupt-parent = <&periph_intc>;
155 reg-io-width = <0x4>;
156 reg-shift = <0x2>;
157 native-endian;
158 interrupt-parent = <&periph_intc>;
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
170 interrupt-names = "upg_bsca";
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
180 interrupt-names = "upg_bscb";
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
190 interrupt-names = "upg_bscc";
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
200 interrupt-names = "upg_bscd";
205 compatible = "brcm,bcm7038-pwm";
207 #pwm-cells = <2>;
214 compatible = "brcm,bcm7038-wdt";
219 aon_pm_l2_intc: interrupt-controller@408440 {
220 compatible = "brcm,l2-intc";
222 interrupt-controller;
223 #interrupt-cells = <1>;
224 interrupt-parent = <&periph_intc>;
226 brcm,irq-can-wake;
230 compatible = "brcm,brcmstb-aon-ctrl";
232 reg-names = "aon-ctrl", "aon-sram";
236 compatible = "brcm,brcmstb-timers";
241 compatible = "brcm,brcmstb-gpio";
243 #gpio-cells = <2>;
244 #interrupt-cells = <2>;
245 gpio-controller;
246 interrupt-controller;
247 interrupt-parent = <&upg_irq0_intc>;
249 brcm,gpio-bank-widths = <32 32 32 29 4>;
253 compatible = "brcm,brcmstb-gpio";
255 #gpio-cells = <2>;
256 #interrupt-cells = <2>;
257 gpio-controller;
258 interrupt-controller;
259 interrupt-parent = <&upg_aon_irq0_intc>;
261 interrupts-extended = <&upg_aon_irq0_intc 6>,
263 wakeup-source;
264 brcm,gpio-bank-widths = <21 32 2>;
268 phy-mode = "internal";
269 phy-handle = <&phy1>;
270 mac-address = [ 00 10 18 36 23 1a ];
271 compatible = "brcm,genet-v2";
272 #address-cells = <0x1>;
273 #size-cells = <0x1>;
276 interrupt-parent = <&periph_intc>;
280 compatible = "brcm,genet-mdio-v2";
281 #address-cells = <0x1>;
282 #size-cells = <0x0>;
285 phy1: ethernet-phy@1 {
286 max-speed = <100>;
288 compatible = "brcm,40nm-ephy",
289 "ethernet-phy-ieee802.3-c22";
295 compatible = "brcm,bcm7360-ehci", "generic-ehci";
297 native-endian;
298 interrupt-parent = <&periph_intc>;
304 compatible = "brcm,bcm7360-ohci", "generic-ohci";
306 native-endian;
307 no-big-frame-no;
308 interrupt-parent = <&periph_intc>;
313 hif_l2_intc: interrupt-controller@411000 {
314 compatible = "brcm,l2-intc";
316 interrupt-controller;
317 #interrupt-cells = <1>;
318 interrupt-parent = <&periph_intc>;
323 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
324 #address-cells = <1>;
325 #size-cells = <0>;
326 reg-names = "nand";
328 interrupt-parent = <&hif_l2_intc>;
334 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
335 reg-names = "ahci", "top-ctrl";
337 interrupt-parent = <&periph_intc>;
339 #address-cells = <1>;
340 #size-cells = <0>;
343 sata0: sata-port@0 {
348 sata1: sata-port@1 {
354 sata_phy: sata-phy@180100 {
355 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
357 reg-names = "phy";
358 #address-cells = <1>;
359 #size-cells = <0>;
362 sata_phy0: sata-phy@0 {
364 #phy-cells = <0>;
367 sata_phy1: sata-phy@1 {
369 #phy-cells = <0>;
374 compatible = "brcm,bcm7425-sdhci";
376 interrupt-parent = <&periph_intc>;
381 spi_l2_intc: interrupt-controller@411d00 {
382 compatible = "brcm,l2-intc";
384 interrupt-controller;
385 #interrupt-cells = <1>;
386 interrupt-parent = <&periph_intc>;
391 #address-cells = <0x1>;
392 #size-cells = <0x0>;
393 compatible = "brcm,spi-bcm-qspi",
394 "brcm,spi-brcmstb-qspi";
397 reg-names = "cs_reg", "hif_mspi", "bspi";
399 interrupt-parent = <&spi_l2_intc>;
400 interrupt-names = "spi_lr_fullness_reached",
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "brcm,spi-bcm-qspi",
414 "brcm,spi-brcmstb-mspi";
417 reg-names = "mspi";
419 interrupt-parent = <&upg_aon_irq0_intc>;
420 interrupt-names = "mspi_done";
425 compatible = "brcm,brcmstb-waketimer";
428 interrupt-parent = <&aon_pm_l2_intc>;
429 interrupt-names = "timer";
436 compatible = "simple-bus";
438 #address-cells = <1>;
439 #size-cells = <1>;
441 memory-controller@0 {
442 compatible = "brcm,brcmstb-memc", "simple-bus";
444 #address-cells = <1>;
445 #size-cells = <1>;
447 memc-arb@1000 {
448 compatible = "brcm,brcmstb-memc-arb";
452 memc-ddr@2000 {
453 compatible = "brcm,brcmstb-memc-ddr";
457 ddr-phy@6000 {
458 compatible = "brcm,brcmstb-ddr-phy";
463 compatible = "brcm,brcmstb-ddr-shimphy";