Lines Matching +full:0 +full:x2600000
9 #size-cells = <0>;
11 cpu@0 {
13 reg = <0>;
60 reg = <0x1800000 0x1000>;
66 reg = <0x01840000 0x8400>;
71 ti,core-mask = < 0x01 >;
72 reg = <0x25e0000 0x40>;
77 ti,core-mask = < 0x02 >;
78 reg = <0x25f0000 0x40>;
83 ti,core-mask = < 0x04 >;
84 reg = <0x2600000 0x40>;
89 ti,core-mask = < 0x08 >;
90 reg = <0x2610000 0x40>;
95 ti,core-mask = < 0x10 >;
96 reg = <0x2620000 0x40>;
101 ti,core-mask = < 0x20 >;
102 reg = <0x2630000 0x40>;
107 reg = <0x029a0000 0x200>;
115 reg = <0x02a80000 0x1000>;
117 ti,dscr-devstat = <0>;
118 ti,dscr-silicon-rev = <0x70c 16 0xff>;
120 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
121 0x704 5 6 0 0>;
123 ti,dscr-rmii-resets = <0x208 1
124 0x20c 1>;
126 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
127 0x40c 0x420 0xbea7
128 0x41c 0x420 0xbea7>;
130 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
132 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;