Lines Matching +full:rx +full:- +full:watermark
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
70 cpu-map {
89 compatible = "arm,cortex-a53";
91 enable-method = "psci";
93 operating-points-v2 = <&cluster0_opp>;
98 compatible = "arm,cortex-a53";
100 enable-method = "psci";
102 operating-points-v2 = <&cluster0_opp>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
111 operating-points-v2 = <&cluster0_opp>;
116 compatible = "arm,cortex-a53";
118 enable-method = "psci";
120 operating-points-v2 = <&cluster0_opp>;
124 cluster0_opp: opp-table0 {
125 compatible = "operating-points-v2";
126 opp-shared;
128 opp-500000000 {
129 opp-hz = /bits/ 64 <500000000>;
130 opp-microvolt = <866000>;
131 clock-latency-ns = <500000>;
134 opp-648000000 {
135 opp-hz = /bits/ 64 <648000000>;
136 opp-microvolt = <866000>;
137 clock-latency-ns = <500000>;
140 opp-800000000 {
141 opp-hz = /bits/ 64 <800000000>;
142 opp-microvolt = <888000>;
143 clock-latency-ns = <500000>;
146 opp-1000000000 {
147 opp-hz = /bits/ 64 <1000000000>;
148 opp-microvolt = <898000>;
149 clock-latency-ns = <500000>;
152 opp-1188000000 {
153 opp-hz = /bits/ 64 <1188000000>;
154 opp-microvolt = <1015000>;
155 clock-latency-ns = <500000>;
159 clk24k: clk-24k {
160 compatible = "fixed-clock";
161 #clock-cells = <0>;
162 clock-frequency = <24000>;
163 clock-output-names = "rtcclk";
166 osc32k: clk-osc32k {
167 compatible = "fixed-clock";
168 #clock-cells = <0>;
169 clock-frequency = <32000>;
170 clock-output-names = "osc32k";
173 osc12m: clk-osc12m {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 clock-frequency = <12000000>;
177 clock-output-names = "osc12m";
180 osc24m: clk-osc24m {
181 compatible = "fixed-clock";
182 #clock-cells = <0>;
183 clock-frequency = <24000000>;
184 clock-output-names = "osc24m";
187 osc25m: clk-osc25m {
188 compatible = "fixed-clock";
189 #clock-cells = <0>;
190 clock-frequency = <25000000>;
191 clock-output-names = "osc25m";
194 osc60m: clk-osc60m {
195 compatible = "fixed-clock";
196 #clock-cells = <0>;
197 clock-frequency = <60000000>;
198 clock-output-names = "osc60m";
201 osc99m: clk-osc99m {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <99000000>;
205 clock-output-names = "osc99m";
208 osc125m: clk-osc125m {
209 compatible = "fixed-clock";
210 #clock-cells = <0>;
211 clock-frequency = <125000000>;
212 clock-output-names = "osc125m";
215 osc198m: clk-osc198m {
216 compatible = "fixed-clock";
217 #clock-cells = <0>;
218 clock-frequency = <198000000>;
219 clock-output-names = "osc198m";
222 pll_audio: clk-pll-884m {
223 compatible = "fixed-clock";
224 #clock-cells = <0>;
225 clock-frequency = <884000000>;
226 clock-output-names = "pll_audio";
229 pll_ddr: clk-pll-932m {
230 compatible = "fixed-clock";
231 #clock-cells = <0>;
232 clock-frequency = <932000000>;
233 clock-output-names = "pll_ddr";
236 pll_hsic: clk-pll-960m {
237 compatible = "fixed-clock";
238 #clock-cells = <0>;
239 clock-frequency = <960000000>;
240 clock-output-names = "pll_hsic";
243 pll_mac: clk-pll-1000m {
244 compatible = "fixed-clock";
245 #clock-cells = <0>;
246 clock-frequency = <1000000000>;
247 clock-output-names = "pll_mac";
250 pll_mm0: clk-pll-1188m {
251 compatible = "fixed-clock";
252 #clock-cells = <0>;
253 clock-frequency = <1188000000>;
254 clock-output-names = "pll_mm0";
257 pll_mm1: clk-pll-1296m {
258 compatible = "fixed-clock";
259 #clock-cells = <0>;
260 clock-frequency = <1296000000>;
261 clock-output-names = "pll_mm1";
265 compatible = "arm,psci-1.0";
270 compatible = "arm,armv8-timer";
278 compatible = "arm,cortex-a53-pmu";
282 gic: interrupt-controller@2a00000 {
283 compatible = "arm,gic-v3";
284 #interrupt-cells = <3>;
285 #address-cells = <0>;
286 interrupt-controller;
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "simple-bus";
298 irdec: ir-decoder@111000 {
299 compatible = "zte,zx296718-irdec";
305 aon_sysctrl: aon-sysctrl@116000 {
306 compatible = "zte,zx296718-aon-sysctrl", "syscon";
310 iocfg: pin-controller@119000 {
311 compatible = "zte,zx296718-iocfg";
317 arm,primecell-periphid = <0x001feffe>;
321 clock-names = "apb_pclk";
326 compatible = "zte,zx296718-dw-mshc";
327 #address-cells = <1>;
328 #size-cells = <0>;
331 fifo-depth = <32>;
332 data-addr = <0x200>;
333 fifo-watermark-aligned;
334 bus-width = <4>;
335 clock-frequency = <50000000>;
337 clock-names = "biu", "ciu";
338 max-frequency = <50000000>;
339 cap-sdio-irq;
340 cap-sd-highspeed;
341 sd-uhs-sdr12;
342 sd-uhs-sdr25;
343 sd-uhs-sdr50;
344 sd-uhs-sdr104;
345 sd-uhs-ddr50;
350 compatible = "zte,zx296718-dw-mshc";
351 #address-cells = <1>;
352 #size-cells = <0>;
355 fifo-depth = <32>;
356 data-addr = <0x200>;
357 fifo-watermark-aligned;
358 bus-width = <4>;
359 clock-frequency = <167000000>;
361 clock-names = "biu", "ciu";
362 max-frequency = <167000000>;
363 cap-sdio-irq;
364 cap-sd-highspeed;
368 dma: dma-controller@1460000 {
369 compatible = "zte,zx296702-dma";
373 clock-names = "dmaclk";
374 #dma-cells = <1>;
375 dma-channels = <32>;
376 dma-requests = <32>;
379 lsp0crm: clock-controller@1420000 {
380 compatible = "zte,zx296718-lsp0crm";
382 #clock-cells = <1>;
386 compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
388 gpio-controller;
389 #gpio-cells = <2>;
390 gpio-ranges = <&pmm 0 48 16>;
392 interrupt-parent = <&gic>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
398 compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
400 gpio-controller;
401 #gpio-cells = <2>;
402 gpio-ranges = <&pmm 0 80 16>;
404 interrupt-parent = <&gic>;
405 interrupt-controller;
406 #interrupt-cells = <2>;
410 compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
412 gpio-controller;
413 #gpio-cells = <2>;
414 gpio-ranges = <&pmm 0 80 3
418 interrupt-parent = <&gic>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
424 compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
426 gpio-controller;
427 #gpio-cells = <2>;
428 gpio-ranges = <&pmm 0 92 16>;
430 interrupt-parent = <&gic>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
436 compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
438 gpio-controller;
439 #gpio-cells = <2>;
440 gpio-ranges = <&pmm 0 108 12
443 interrupt-parent = <&gic>;
444 interrupt-controller;
445 #interrupt-cells = <2>;
449 compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
451 gpio-controller;
452 #gpio-cells = <2>;
453 gpio-ranges = <&pmm 0 125 16>;
455 interrupt-parent = <&gic>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
461 compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
463 gpio-controller;
464 #gpio-cells = <2>;
465 gpio-ranges = <&pmm 0 141 2>;
467 interrupt-parent = <&gic>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
472 lsp1crm: clock-controller@1430000 {
473 compatible = "zte,zx296718-lsp1crm";
475 #clock-cells = <1>;
479 compatible = "zte,zx296718-pwm";
483 clock-names = "pclk", "wclk";
484 #pwm-cells = <3>;
489 compatible = "zte,zx296718-vou";
490 #address-cells = <1>;
491 #size-cells = <1>;
495 compatible = "zte,zx296718-dpc";
499 reg-names = "osd", "timing_ctrl",
505 clock-names = "aclk", "ppu_wclk",
510 compatible = "zte,zx296718-vga";
514 clock-names = "i2c_wclk";
515 zte,vga-power-control = <&sysctrl 0x170 0xe0>;
520 compatible = "zte,zx296718-hdmi";
526 clock-names = "osc_cec", "osc_clk", "xclk";
527 #sound-dai-cells = <0>;
532 compatible = "zte,zx296718-tvenc";
534 zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
539 topcrm: clock-controller@1461000 {
540 compatible = "zte,zx296718-topcrm";
542 #clock-cells = <1>;
545 pmm: pin-controller@1462000 {
546 compatible = "zte,zx296718-pmm";
548 zte,auxiliary-controller = <&iocfg>;
552 compatible = "zte,zx296718-sysctrl", "syscon";
557 compatible = "zte,zx296718-dw-mshc";
560 zte,aon-syscon = <&aon_sysctrl>;
561 bus-width = <8>;
562 fifo-depth = <128>;
563 data-addr = <0x200>;
564 fifo-watermark-aligned;
565 clock-frequency = <167000000>;
567 clock-names = "biu", "ciu";
568 max-frequency = <167000000>;
569 cap-mmc-highspeed;
570 mmc-ddr-1_8v;
571 mmc-hs200-1_8v;
572 non-removable;
573 disable-wp;
577 audiocrm: clock-controller@1480000 {
578 compatible = "zte,zx296718-audiocrm";
580 #clock-cells = <1>;
584 compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
588 clock-names = "wclk", "pclk";
589 assigned-clocks = <&audiocrm I2S0_WCLK_MUX>;
590 assigned-clock-parents = <&topcrm AUDIO_99M>;
593 dma-names = "tx", "rx";
594 #sound-dai-cells = <0>;
599 compatible = "zte,zx296718-i2c";
602 #address-cells = <1>;
603 #size-cells = <0>;
605 clock-frequency = <1600000>;
609 compatible = "zte,zx-aud96p22";
610 #sound-dai-cells = <0>;
616 compatible = "zte,zx296702-spdif";
619 clock-names = "tx";
621 #sound-dai-cells = <0>;
623 dma-names = "tx";