Lines Matching +full:0 +full:xfd510000
29 #size-cells = <0>;
31 cpu0: cpu@0 {
36 reg = <0x0>;
45 reg = <0x1>;
55 reg = <0x2>;
65 reg = <0x3>;
80 CPU_SLEEP_0: cpu-sleep-0 {
82 arm,psci-suspend-param = <0x40000000>;
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
137 xlnx,ipi-id = <0>;
145 reg = <0x0 0xff9905c0 0x0 0x20>,
146 <0x0 0xff9905e0 0x0 0x20>,
147 <0x0 0xff990e80 0x0 0x20>,
148 <0x0 0xff990ea0 0x0 0x20>;
194 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
203 soc_revision: soc-revision@0 {
204 reg = <0x0 0x4>;
255 r5f-0 {
279 reg = <0x0 0xff060000 0x0 0x1000>;
282 tx-fifo-depth = <0x40>;
283 rx-fifo-depth = <0x40>;
291 reg = <0x0 0xff070000 0x0 0x1000>;
294 tx-fifo-depth = <0x40>;
295 rx-fifo-depth = <0x40>;
302 reg = <0x0 0xfd6e0000 0x0 0x9000>;
303 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
309 reg = <0x9000 0x5000>;
323 reg = <0x0 0xfd500000 0x0 0x1000>;
329 iommus = <&smmu 0x14e8>;
336 reg = <0x0 0xfd510000 0x0 0x1000>;
342 iommus = <&smmu 0x14e9>;
349 reg = <0x0 0xfd520000 0x0 0x1000>;
355 iommus = <&smmu 0x14ea>;
362 reg = <0x0 0xfd530000 0x0 0x1000>;
368 iommus = <&smmu 0x14eb>;
375 reg = <0x0 0xfd540000 0x0 0x1000>;
381 iommus = <&smmu 0x14ec>;
388 reg = <0x0 0xfd550000 0x0 0x1000>;
394 iommus = <&smmu 0x14ed>;
401 reg = <0x0 0xfd560000 0x0 0x1000>;
407 iommus = <&smmu 0x14ee>;
414 reg = <0x0 0xfd570000 0x0 0x1000>;
420 iommus = <&smmu 0x14ef>;
427 reg = <0x0 0xf9010000 0x0 0x10000>,
428 <0x0 0xf9020000 0x0 0x20000>,
429 <0x0 0xf9040000 0x0 0x20000>,
430 <0x0 0xf9060000 0x0 0x20000>;
439 reg = <0x0 0xfd4b0000 0x0 0x10000>;
459 reg = <0x0 0xffa80000 0x0 0x1000>;
465 iommus = <&smmu 0x868>;
472 reg = <0x0 0xffa90000 0x0 0x1000>;
478 iommus = <&smmu 0x869>;
485 reg = <0x0 0xffaa0000 0x0 0x1000>;
491 iommus = <&smmu 0x86a>;
498 reg = <0x0 0xffab0000 0x0 0x1000>;
504 iommus = <&smmu 0x86b>;
511 reg = <0x0 0xffac0000 0x0 0x1000>;
517 iommus = <&smmu 0x86c>;
524 reg = <0x0 0xffad0000 0x0 0x1000>;
530 iommus = <&smmu 0x86d>;
537 reg = <0x0 0xffae0000 0x0 0x1000>;
543 iommus = <&smmu 0x86e>;
550 reg = <0x0 0xffaf0000 0x0 0x1000>;
556 iommus = <&smmu 0x86f>;
562 reg = <0x0 0xfd070000 0x0 0x30000>;
570 reg = <0x0 0xff100000 0x0 0x1000>;
575 #size-cells = <0>;
576 iommus = <&smmu 0x872>;
586 reg = <0x0 0xff0b0000 0x0 0x1000>;
588 iommus = <&smmu 0x874>;
600 reg = <0x0 0xff0c0000 0x0 0x1000>;
602 iommus = <&smmu 0x875>;
614 reg = <0x0 0xff0d0000 0x0 0x1000>;
616 iommus = <&smmu 0x876>;
628 reg = <0x0 0xff0e0000 0x0 0x1000>;
630 iommus = <&smmu 0x877>;
639 #gpio-cells = <0x2>;
645 reg = <0x0 0xff0a0000 0x0 0x1000>;
655 reg = <0x0 0xff020000 0x0 0x1000>;
657 #size-cells = <0>;
667 reg = <0x0 0xff030000 0x0 0x1000>;
669 #size-cells = <0>;
686 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
690 reg = <0x0 0xfd0e0000 0x0 0x1000>,
691 <0x0 0xfd480000 0x0 0x1000>,
692 <0x80 0x00000000 0x0 0x1000000>;
694 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
695 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
696 bus-range = <0x00 0xff>;
697 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
698 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
699 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
700 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
701 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
702 iommus = <&smmu 0x4d0>;
706 #address-cells = <0>;
719 reg = <0x0 0xff0f0000 0x0 0x1000>,
720 <0x0 0xc0000000 0x0 0x8000000>;
722 #size-cells = <0>;
723 iommus = <&smmu 0x873>;
730 reg = <0x0 0xfd400000 0x0 0x40000>,
731 <0x0 0xfd3d0000 0x0 0x1000>;
739 reg = <0x0 0xffa60000 0x0 0x100>;
744 calibration = <0x7FFF>;
750 reg = <0x0 0xfd0c0000 0x0 0x2000>;
755 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
756 <&smmu 0x4c2>, <&smmu 0x4c3>;
765 reg = <0x0 0xff160000 0x0 0x1000>;
767 iommus = <&smmu 0x870>;
780 reg = <0x0 0xff170000 0x0 0x1000>;
782 iommus = <&smmu 0x871>;
791 reg = <0x0 0xfd800000 0x0 0x20000>;
820 reg = <0x0 0xff040000 0x0 0x1000>;
823 #size-cells = <0>;
832 reg = <0x0 0xff050000 0x0 0x1000>;
835 #size-cells = <0>;
846 reg = <0x0 0xff110000 0x0 0x1000>;
858 reg = <0x0 0xff120000 0x0 0x1000>;
870 reg = <0x0 0xff130000 0x0 0x1000>;
882 reg = <0x0 0xff140000 0x0 0x1000>;
893 reg = <0x0 0xff000000 0x0 0x1000>;
904 reg = <0x0 0xff010000 0x0 0x1000>;
914 reg = <0x0 0xff9d0000 0x0 0x100>;
925 reg = <0x0 0xfe200000 0x0 0x40000>;
932 iommus = <&smmu 0x860>;
933 snps,quirk-frame-length-adjustment = <0x20>;
944 reg = <0x0 0xff9e0000 0x0 0x100>;
954 reg = <0x0 0xfe300000 0x0 0x40000>;
961 iommus = <&smmu 0x861>;
962 snps,quirk-frame-length-adjustment = <0x20>;
973 reg = <0x0 0xfd4d0000 0x0 0x1000>;
983 reg = <0x0 0xff150000 0x0 0x1000>;
992 reg = <0x0 0xffa50000 0x0 0x800>;
996 ranges = <0 0 0xffa50800 0x800>;
998 ams_ps: ams-ps@0 {
1001 reg = <0x0 0x400>;
1007 reg = <0x400 0x400>;
1009 #size-cells = <0>;
1016 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1028 reg = <0x0 0xfd4a0000 0x0 0x1000>,
1029 <0x0 0xfd4aa000 0x0 0x1000>,
1030 <0x0 0xfd4ab000 0x0 0x1000>,
1031 <0x0 0xfd4ac000 0x0 0x1000>;
1047 #size-cells = <0>;
1049 port@0 {
1050 reg = <0>;