Lines Matching +full:rb +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
35 stdout-path = "serial0:115200n8";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_can0_default>;
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_can1_default>;
90 phy-handle = <&phy0>;
91 phy-mode = "rgmii-id";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gem2_default>;
95 #address-cells = <1>;
96 #size-cells = <0>;
97 phy0: ethernet-phy@5 {
99 ti,rx-internal-delay = <0x8>;
100 ti,tx-internal-delay = <0xa>;
101 ti,fifo-depth = <0x1>;
102 ti,dp83867-rxctrl-strap-quirk;
113 clock-frequency = <400000>;
114 pinctrl-names = "default", "gpio";
115 pinctrl-0 = <&pinctrl_i2c0_default>;
116 pinctrl-1 = <&pinctrl_i2c0_gpio>;
117 scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
118 sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
123 gpio-controller;
124 #gpio-cells = <2>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_nand0_default>;
138 arasan,has-mdma;
142 #address-cells = <0x2>;
143 #size-cells = <0x1>;
144 nand-ecc-mode = "soft";
145 nand-ecc-algo = "bch";
146 nand-rb = <0>;
147 label = "main-storage-0";
151 #address-cells = <0x2>;
152 #size-cells = <0x1>;
153 nand-ecc-mode = "soft";
154 nand-ecc-algo = "bch";
155 nand-rb = <0>;
156 label = "main-storage-1";
162 pinctrl_can0_default: can0-default {
170 slew-rate = <SLEW_RATE_SLOW>;
171 power-source = <IO_STANDARD_LVCMOS18>;
174 conf-rx {
176 bias-high-impedance;
179 conf-tx {
181 bias-disable;
185 pinctrl_can1_default: can1-default {
193 slew-rate = <SLEW_RATE_SLOW>;
194 power-source = <IO_STANDARD_LVCMOS18>;
197 conf-rx {
199 bias-high-impedance;
202 conf-tx {
204 bias-disable;
208 pinctrl_i2c0_default: i2c0-default {
216 bias-pull-up;
217 slew-rate = <SLEW_RATE_SLOW>;
218 power-source = <IO_STANDARD_LVCMOS18>;
222 pinctrl_i2c0_gpio: i2c0-gpio {
230 slew-rate = <SLEW_RATE_SLOW>;
231 power-source = <IO_STANDARD_LVCMOS18>;
235 pinctrl_uart0_default: uart0-default {
243 slew-rate = <SLEW_RATE_SLOW>;
244 power-source = <IO_STANDARD_LVCMOS18>;
247 conf-rx {
249 bias-high-impedance;
252 conf-tx {
254 bias-disable;
258 pinctrl_uart1_default: uart1-default {
266 slew-rate = <SLEW_RATE_SLOW>;
267 power-source = <IO_STANDARD_LVCMOS18>;
270 conf-rx {
272 bias-high-impedance;
275 conf-tx {
277 bias-disable;
281 pinctrl_usb1_default: usb1-default {
289 power-source = <IO_STANDARD_LVCMOS18>;
292 conf-rx {
294 bias-high-impedance;
295 drive-strength = <12>;
296 slew-rate = <SLEW_RATE_FAST>;
299 conf-tx {
302 bias-disable;
303 drive-strength = <4>;
304 slew-rate = <SLEW_RATE_SLOW>;
308 pinctrl_gem2_default: gem2-default {
316 slew-rate = <SLEW_RATE_SLOW>;
317 power-source = <IO_STANDARD_LVCMOS18>;
320 conf-rx {
323 bias-high-impedance;
324 low-power-disable;
327 conf-tx {
330 bias-disable;
331 low-power-enable;
334 mux-mdio {
339 conf-mdio {
341 slew-rate = <SLEW_RATE_SLOW>;
342 power-source = <IO_STANDARD_LVCMOS18>;
343 bias-disable;
347 pinctrl_nand0_default: nand0-default {
355 bias-pull-up;
358 mux-ce {
363 conf-ce {
365 bias-pull-up;
368 mux-rb {
373 conf-rb {
375 bias-pull-up;
378 mux-dqs {
383 conf-dqs {
385 bias-pull-up;
389 pinctrl_spi0_default: spi0-default {
397 bias-disable;
398 slew-rate = <SLEW_RATE_SLOW>;
399 power-source = <IO_STANDARD_LVCMOS18>;
402 mux-cs {
408 conf-cs {
411 bias-disable;
415 pinctrl_spi1_default: spi1-default {
423 bias-disable;
424 slew-rate = <SLEW_RATE_SLOW>;
425 power-source = <IO_STANDARD_LVCMOS18>;
428 mux-cs {
434 conf-cs {
437 bias-disable;
448 num-cs = <1>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_spi0_default>;
453 #address-cells = <1>;
454 #size-cells = <1>;
455 compatible = "sst,sst25wf080", "jedec,spi-nor";
456 spi-max-frequency = <50000000>;
460 label = "spi0-data";
468 num-cs = <1>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_spi1_default>;
473 #address-cells = <1>;
474 #size-cells = <1>;
476 spi-max-frequency = <20000000>;
480 label = "spi1-data";
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_usb1_default>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_uart0_default>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_uart1_default>;