Lines Matching +full:fw +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP SM-K26 Rev1/B/A";
21 compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
22 "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
45 stdout-path = "serial1:115200n8";
53 reserved-memory {
54 #address-cells = <2>;
55 #size-cells = <2>;
60 no-map;
64 gpio-keys {
65 compatible = "gpio-keys";
67 key-fwuen {
69 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
71 wakeup-source;
77 compatible = "gpio-leds";
78 ds35-led {
80 gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
81 linux,default-trigger = "heartbeat";
84 ds36-led {
86 gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
87 default-state = "on";
92 compatible = "iio-hwmon";
93 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
116 pinctrl_sdhci0_default: sdhci0-default {
119 slew-rate = <SLEW_RATE_SLOW>;
120 power-source = <IO_STANDARD_LVCMOS18>;
121 bias-disable;
131 &qspi { /* MIO 0-5 - U143 */
134 compatible = "jedec,spi-nor"; /* 64MB */
136 spi-tx-bus-width = <4>;
137 spi-rx-bus-width = <4>;
138 spi-max-frequency = <40000000>; /* 40MHz */
141 compatible = "fixed-partitions";
142 #address-cells = <1>;
143 #size-cells = <1>;
148 read-only;
154 read-only;
170 label = "Image A (FSBL, PMU, ATF, U-Boot)";
176 read-only;
180 label = "Image B (FSBL, PMU, ATF, U-Boot)";
186 read-only;
196 read-only;
202 read-only;
206 label = "U-Boot storage variables";
210 label = "U-Boot storage variables backup";
216 read-only;
231 &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_sdhci0_default>;
235 non-removable;
236 disable-wp;
237 bus-width = <8>;
238 xlnx,mio-bank = <0>;
239 assigned-clock-rates = <187498123>;
242 &spi1 { /* MIO6, 9-11 */
245 num-cs = <1>;
246 tpm@0 { /* slm9670 - U144 */
247 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
249 spi-max-frequency = <18500000>;
255 bootph-all;
256 clock-frequency = <400000>;
257 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
258 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
260 eeprom: eeprom@50 { /* u46 - also at address 0x58 */
261 bootph-all;
267 eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
268 bootph-all;
273 /* da9062@30 - u170 - also at address 0x31 */
274 /* da9131@33 - u167 */
280 regulator-name = "da9131_buck1";
281 regulator-boot-on;
282 regulator-always-on;
285 regulator-name = "da9131_buck2";
286 regulator-boot-on;
287 regulator-always-on;
292 /* da9130@32 - u166 */
298 regulator-name = "da9130_buck1";
299 regulator-boot-on;
300 regulator-always-on;
305 /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
307 * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
310 * With the FW fix, stdp4320 should respond to address 0x73 only.
312 /* slg7x644092@68 - u169 */
318 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
319 "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
320 "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
321 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
322 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
323 "I2C1_SDA", "", "", "", "", /* 25 - 29 */
324 "", "", "", "", "", /* 30 - 34 */
325 "", "", "", "", "", /* 35 - 39 */
326 "", "", "", "", "", /* 40 - 44 */
327 "", "", "", "", "", /* 45 - 49 */
328 "", "", "", "", "", /* 50 - 54 */
329 "", "", "", "", "", /* 55 - 59 */
330 "", "", "", "", "", /* 60 - 64 */
331 "", "", "", "", "", /* 65 - 69 */
332 "", "", "", "", "", /* 70 - 74 */
333 "", "", "", /* 75 - 77, MIO end and EMIO start */
334 "", "", /* 78 - 79 */
335 "", "", "", "", "", /* 80 - 84 */
336 "", "", "", "", "", /* 85 - 89 */
337 "", "", "", "", "", /* 90 - 94 */
338 "", "", "", "", "", /* 95 - 99 */
339 "", "", "", "", "", /* 100 - 104 */
340 "", "", "", "", "", /* 105 - 109 */
341 "", "", "", "", "", /* 110 - 114 */
342 "", "", "", "", "", /* 115 - 119 */
343 "", "", "", "", "", /* 120 - 124 */
344 "", "", "", "", "", /* 125 - 129 */
345 "", "", "", "", "", /* 130 - 134 */
346 "", "", "", "", "", /* 135 - 139 */
347 "", "", "", "", "", /* 140 - 144 */
348 "", "", "", "", "", /* 145 - 149 */
349 "", "", "", "", "", /* 150 - 154 */
350 "", "", "", "", "", /* 155 - 159 */
351 "", "", "", "", "", /* 160 - 164 */
352 "", "", "", "", "", /* 165 - 169 */
353 "", "", "", ""; /* 170 - 173 */
454 opp-hz = /bits/ 64 <1333333333>;
457 opp-hz = /bits/ 64 <666666666>;
460 opp-hz = /bits/ 64 <444444444>;
463 opp-hz = /bits/ 64 <333333333>;