Lines Matching +full:level +full:- +full:shifter
1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
21 pinctrl-names = "default", "gpio";
22 pinctrl-0 = <&pinctrl_i2c1_default>;
23 pinctrl-1 = <&pinctrl_i2c1_gpio>;
24 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
25 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
27 /* u14 - 0x40 - ina260 */
28 /* u43 - 0x2d - usb5744 */
29 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <125000000>;
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <25000000>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <48000000>;
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <24000000>;
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <26000000>;
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <27000000>;
75 clock-names = "ref0", "ref1", "ref2";
80 phy-names = "dp-phy0", "dp-phy1";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_usb0_default>;
92 phy-names = "usb3-phy";
100 maximum-speed = "super-speed";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_sdhci1_default>;
108 * SD 3.0 requires level shifter and this property
109 * should be removed if the board has level shifter and
112 no-1-8-v;
113 disable-wp;
114 xlnx,mio-bank = <1>;
115 clk-phase-sd-hs = <126>, <60>;
116 clk-phase-uhs-sdr25 = <120>, <60>;
117 clk-phase-uhs-ddr50 = <126>, <48>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_gem3_default>;
124 phy-handle = <&phy0>;
125 phy-mode = "rgmii-id";
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
131 reset-delay-us = <2>;
133 phy0: ethernet-phy@1 {
134 #phy-cells = <1>;
136 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
137 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
138 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
139 ti,dp83867-rxctrl-strap-quirk;
147 pinctrl_uart1_default: uart1-default {
150 slew-rate = <SLEW_RATE_SLOW>;
151 power-source = <IO_STANDARD_LVCMOS18>;
152 drive-strength = <12>;
155 conf-rx {
157 bias-high-impedance;
160 conf-tx {
162 bias-disable;
171 pinctrl_i2c1_default: i2c1-default {
174 bias-pull-up;
175 slew-rate = <SLEW_RATE_SLOW>;
176 power-source = <IO_STANDARD_LVCMOS18>;
185 pinctrl_i2c1_gpio: i2c1-gpio {
188 slew-rate = <SLEW_RATE_SLOW>;
189 power-source = <IO_STANDARD_LVCMOS18>;
198 pinctrl_gem3_default: gem3-default {
201 slew-rate = <SLEW_RATE_SLOW>;
202 power-source = <IO_STANDARD_LVCMOS18>;
205 conf-rx {
207 bias-high-impedance;
208 low-power-disable;
211 conf-bootstrap {
213 bias-disable;
214 low-power-disable;
217 conf-tx {
220 bias-disable;
221 low-power-enable;
224 conf-mdio {
226 slew-rate = <SLEW_RATE_SLOW>;
227 power-source = <IO_STANDARD_LVCMOS18>;
228 bias-disable;
231 mux-mdio {
242 pinctrl_usb0_default: usb0-default {
245 slew-rate = <SLEW_RATE_SLOW>;
246 power-source = <IO_STANDARD_LVCMOS18>;
249 conf-rx {
251 bias-high-impedance;
254 conf-tx {
257 bias-disable;
266 pinctrl_sdhci1_default: sdhci1-default {
269 slew-rate = <SLEW_RATE_SLOW>;
270 power-source = <IO_STANDARD_LVCMOS18>;
271 bias-disable;
274 conf-cd {
276 bias-high-impedance;
277 bias-pull-up;
278 slew-rate = <SLEW_RATE_SLOW>;
279 power-source = <IO_STANDARD_LVCMOS18>;
282 mux-cd {
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_uart1_default>;