Lines Matching +full:level +full:- +full:shifter
1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * SD level shifter:
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
21 /dts-v1/;
25 si5332_0: si5332-0 { /* u17 */
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <125000000>;
31 si5332_1: si5332-1 { /* u17 */
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <25000000>;
37 si5332_2: si5332-2 { /* u17 */
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <48000000>;
43 si5332_3: si5332-3 { /* u17 */
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <24000000>;
49 si5332_4: si5332-4 { /* u17 */
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <26000000>;
55 si5332_5: si5332-5 { /* u17 */
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <27000000>;
62 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
63 #address-cells = <1>;
64 #size-cells = <0>;
65 pinctrl-names = "default", "gpio";
66 pinctrl-0 = <&pinctrl_i2c1_default>;
67 pinctrl-1 = <&pinctrl_i2c1_gpio>;
68 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
69 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
71 /* u14 - 0x40 - ina260 */
72 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
80 clock-names = "ref0", "ref1", "ref2";
86 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
87 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
88 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
89 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
90 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
91 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
92 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
93 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
94 phy-names = "sata-phy";
100 phy-names = "dp-phy0", "dp-phy1";
102 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
107 assigned-clock-rates = <600000000>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_usb0_default>;
114 phy-names = "usb3-phy";
116 /* missing usb5744 - u43 */
123 maximum-speed = "super-speed";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_sdhci1_default>;
131 * SD 3.0 requires level shifter and this property
132 * should be removed if the board has level shifter and
135 no-1-8-v;
136 disable-wp;
137 xlnx,mio-bank = <1>;
138 assigned-clock-rates = <187498123>;
139 bus-width = <4>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_gem3_default>;
146 phy-handle = <&phy0>;
147 phy-mode = "rgmii-id";
148 assigned-clock-rates = <250000000>;
151 #address-cells = <1>;
152 #size-cells = <0>;
154 phy0: ethernet-phy@1 {
155 #phy-cells = <1>;
157 compatible = "ethernet-phy-id2000.a231";
158 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
159 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
160 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
161 ti,dp83867-rxctrl-strap-quirk;
162 reset-assert-us = <100>;
163 reset-deassert-us = <280>;
164 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
172 pinctrl_uart1_default: uart1-default {
175 slew-rate = <SLEW_RATE_SLOW>;
176 power-source = <IO_STANDARD_LVCMOS18>;
177 drive-strength = <12>;
180 conf-rx {
182 bias-high-impedance;
185 conf-tx {
187 bias-disable;
196 pinctrl_i2c1_default: i2c1-default {
199 bias-pull-up;
200 slew-rate = <SLEW_RATE_SLOW>;
201 power-source = <IO_STANDARD_LVCMOS18>;
210 pinctrl_i2c1_gpio: i2c1-gpio {
213 slew-rate = <SLEW_RATE_SLOW>;
214 power-source = <IO_STANDARD_LVCMOS18>;
223 pinctrl_gem3_default: gem3-default {
226 slew-rate = <SLEW_RATE_SLOW>;
227 power-source = <IO_STANDARD_LVCMOS18>;
230 conf-rx {
232 bias-high-impedance;
233 low-power-disable;
236 conf-bootstrap {
238 bias-disable;
239 low-power-disable;
242 conf-tx {
245 bias-disable;
246 low-power-enable;
249 conf-mdio {
251 slew-rate = <SLEW_RATE_SLOW>;
252 power-source = <IO_STANDARD_LVCMOS18>;
253 bias-disable;
256 mux-mdio {
267 pinctrl_usb0_default: usb0-default {
270 power-source = <IO_STANDARD_LVCMOS18>;
273 conf-rx {
275 bias-high-impedance;
276 drive-strength = <12>;
277 slew-rate = <SLEW_RATE_FAST>;
280 conf-tx {
283 bias-disable;
284 drive-strength = <4>;
285 slew-rate = <SLEW_RATE_SLOW>;
294 pinctrl_sdhci1_default: sdhci1-default {
297 slew-rate = <SLEW_RATE_SLOW>;
298 power-source = <IO_STANDARD_LVCMOS18>;
299 bias-disable;
302 conf-cd {
304 bias-high-impedance;
305 bias-pull-up;
306 slew-rate = <SLEW_RATE_SLOW>;
307 power-source = <IO_STANDARD_LVCMOS18>;
310 mux-cd {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_uart1_default>;