Lines Matching +full:usb +full:- +full:plugin
1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
8 * "A" – A01 board un-modified (NXP)
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 /dts-v1/;
21 /plugin/;
23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
24 #address-cells = <1>;
25 #size-cells = <0>;
26 pinctrl-names = "default", "gpio";
27 pinctrl-0 = <&pinctrl_i2c1_default>;
28 pinctrl-1 = <&pinctrl_i2c1_gpio>;
29 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
30 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
32 /* u14 - 0x40 - ina260 */
33 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <125000000>;
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <48000000>;
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <24000000>;
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <26000000>;
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <27000000>;
74 /* DP/USB 3.0 and SATA */
79 clock-names = "ref0", "ref1", "ref2";
85 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
86 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
87 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
88 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
89 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
90 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
91 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
92 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
93 phy-names = "sata-phy";
99 phy-names = "dp-phy0", "dp-phy1";
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_usb0_default>;
111 phy-names = "usb3-phy";
113 /* missing usb5744 - u43 */
120 maximum-speed = "super-speed";
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_sdhci1_default>;
132 no-1-8-v;
133 disable-wp;
134 xlnx,mio-bank = <1>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_gem3_default>;
141 phy-handle = <&phy0>;
142 phy-mode = "rgmii-id";
145 #address-cells = <1>;
146 #size-cells = <0>;
147 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
148 reset-delay-us = <2>;
150 phy0: ethernet-phy@1 {
151 #phy-cells = <1>;
153 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
154 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
155 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
156 ti,dp83867-rxctrl-strap-quirk;
164 pinctrl_uart1_default: uart1-default {
167 slew-rate = <SLEW_RATE_SLOW>;
168 power-source = <IO_STANDARD_LVCMOS18>;
169 drive-strength = <12>;
172 conf-rx {
174 bias-high-impedance;
177 conf-tx {
179 bias-disable;
188 pinctrl_i2c1_default: i2c1-default {
191 bias-pull-up;
192 slew-rate = <SLEW_RATE_SLOW>;
193 power-source = <IO_STANDARD_LVCMOS18>;
202 pinctrl_i2c1_gpio: i2c1-gpio {
205 slew-rate = <SLEW_RATE_SLOW>;
206 power-source = <IO_STANDARD_LVCMOS18>;
215 pinctrl_gem3_default: gem3-default {
218 slew-rate = <SLEW_RATE_SLOW>;
219 power-source = <IO_STANDARD_LVCMOS18>;
222 conf-rx {
224 bias-high-impedance;
225 low-power-disable;
228 conf-bootstrap {
230 bias-disable;
231 low-power-disable;
234 conf-tx {
237 bias-disable;
238 low-power-enable;
241 conf-mdio {
243 slew-rate = <SLEW_RATE_SLOW>;
244 power-source = <IO_STANDARD_LVCMOS18>;
245 bias-disable;
248 mux-mdio {
259 pinctrl_usb0_default: usb0-default {
262 slew-rate = <SLEW_RATE_SLOW>;
263 power-source = <IO_STANDARD_LVCMOS18>;
266 conf-rx {
268 bias-high-impedance;
271 conf-tx {
274 bias-disable;
283 pinctrl_sdhci1_default: sdhci1-default {
286 slew-rate = <SLEW_RATE_SLOW>;
287 power-source = <IO_STANDARD_LVCMOS18>;
288 bias-disable;
291 conf-cd {
293 bias-high-impedance;
294 bias-pull-up;
295 slew-rate = <SLEW_RATE_SLOW>;
296 power-source = <IO_STANDARD_LVCMOS18>;
299 mux-cd {
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_uart1_default>;