Lines Matching +full:0 +full:x42040000
26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
101 d-cache-size = <0x8000>;
109 reg = <0x003>;
112 i-cache-size = <0xc000>;
115 d-cache-size = <0x8000>;
123 reg = <0x100>;
126 i-cache-size = <0xc000>;
129 d-cache-size = <0x8000>;
137 reg = <0x101>;
140 i-cache-size = <0xc000>;
143 d-cache-size = <0x8000>;
151 reg = <0x102>;
154 i-cache-size = <0xc000>;
157 d-cache-size = <0x8000>;
165 reg = <0x103>;
168 i-cache-size = <0xc000>;
171 d-cache-size = <0x8000>;
182 cache-size = <0x200000>;
192 cache-size = <0x200000>;
235 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
236 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
237 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
238 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
239 <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
240 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
241 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
242 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
243 <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
244 <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
245 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
246 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
247 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
248 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
249 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
252 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
253 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
254 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
255 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
256 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
257 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
258 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
259 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
260 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
261 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
262 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
263 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
264 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
271 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
272 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
273 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
274 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
275 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
276 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
277 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
278 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
279 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
280 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
281 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
282 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
283 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/