Lines Matching +full:timer +full:- +full:secure
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 bootph-all;
11 compatible = "ti,k2g-sci";
12 ti,host-id = <12>;
14 mbox-names = "rx", "tx";
19 reg-names = "debug_messages";
22 k3_pds: power-controller {
23 bootph-all;
24 compatible = "ti,sci-pm-domain";
25 #power-domain-cells = <2>;
28 k3_clks: clock-controller {
29 bootph-all;
30 compatible = "ti,k2g-sci-clk";
31 #clock-cells = <2>;
34 k3_reset: reset-controller {
35 bootph-all;
36 compatible = "ti,sci-reset";
37 #reset-cells = <2>;
42 bootph-all;
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
49 bootph-all;
50 compatible = "ti,am654-chipid";
56 compatible = "ti,am654-secure-proxy";
57 #mbox-cells = <1>;
58 reg-names = "target_data", "rt", "scfg";
65 * firmware on non-MPU processors
71 compatible = "mmio-sram";
74 #address-cells = <1>;
75 #size-cells = <1>;
79 compatible = "pinctrl-single";
82 #pinctrl-cells = <1>;
83 pinctrl-single,register-width = <32>;
84 pinctrl-single,function-mask = <0xffffffff>;
88 compatible = "pinctrl-single";
91 #pinctrl-cells = <1>;
92 pinctrl-single,register-width = <32>;
93 pinctrl-single,function-mask = <0xffffffff>;
97 compatible = "pinctrl-single";
100 #pinctrl-cells = <1>;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0xffffffff>;
106 compatible = "pinctrl-single";
109 #pinctrl-cells = <1>;
110 pinctrl-single,register-width = <32>;
111 pinctrl-single,function-mask = <0xffffffff>;
114 wkup_gpio_intr: interrupt-controller@42200000 {
115 compatible = "ti,sci-intr";
117 ti,intr-trigger-type = <1>;
118 interrupt-controller;
119 interrupt-parent = <&gic500>;
120 #interrupt-cells = <1>;
122 ti,sci-dev-id = <177>;
123 ti,interrupt-ranges = <16 960 16>;
128 compatible = "pinctrl-single";
130 #pinctrl-cells = <1>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x0000000f>;
133 /* Non-MPU Firmware usage */
139 compatible = "pinctrl-single";
141 #pinctrl-cells = <1>;
142 pinctrl-single,register-width = <32>;
143 pinctrl-single,function-mask = <0x0000000f>;
144 /* Non-MPU Firmware usage */
149 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
151 #address-cells = <1>;
152 #size-cells = <1>;
156 compatible = "ti,am654-phy-gmii-sel";
158 #phy-cells = <1>;
162 mcu_timer0: timer@40400000 {
163 compatible = "ti,am654-timer";
167 clock-names = "fck";
168 assigned-clocks = <&k3_clks 35 2>;
169 assigned-clock-parents = <&k3_clks 35 3>;
170 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
171 ti,timer-pwm;
172 /* Non-MPU Firmware usage */
176 mcu_timer1: timer@40410000 {
177 bootph-all;
178 compatible = "ti,am654-timer";
182 clock-names = "fck";
183 assigned-clocks = <&k3_clks 117 2>;
184 assigned-clock-parents = <&k3_clks 117 3>;
185 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
186 ti,timer-pwm;
187 /* Non-MPU Firmware usage */
191 mcu_timer2: timer@40420000 {
192 compatible = "ti,am654-timer";
196 clock-names = "fck";
197 assigned-clocks = <&k3_clks 118 2>;
198 assigned-clock-parents = <&k3_clks 118 3>;
199 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>;
200 ti,timer-pwm;
201 /* Non-MPU Firmware usage */
205 mcu_timer3: timer@40430000 {
206 compatible = "ti,am654-timer";
210 clock-names = "fck";
211 assigned-clocks = <&k3_clks 119 2>;
212 assigned-clock-parents = <&k3_clks 119 3>;
213 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
214 ti,timer-pwm;
215 /* Non-MPU Firmware usage */
219 mcu_timer4: timer@40440000 {
220 compatible = "ti,am654-timer";
224 clock-names = "fck";
225 assigned-clocks = <&k3_clks 120 2>;
226 assigned-clock-parents = <&k3_clks 120 3>;
227 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
228 ti,timer-pwm;
229 /* Non-MPU Firmware usage */
233 mcu_timer5: timer@40450000 {
234 compatible = "ti,am654-timer";
238 clock-names = "fck";
239 assigned-clocks = <&k3_clks 121 2>;
240 assigned-clock-parents = <&k3_clks 121 3>;
241 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
242 ti,timer-pwm;
243 /* Non-MPU Firmware usage */
247 mcu_timer6: timer@40460000 {
248 compatible = "ti,am654-timer";
252 clock-names = "fck";
253 assigned-clocks = <&k3_clks 122 2>;
254 assigned-clock-parents = <&k3_clks 122 3>;
255 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>;
256 ti,timer-pwm;
257 /* Non-MPU Firmware usage */
261 mcu_timer7: timer@40470000 {
262 compatible = "ti,am654-timer";
266 clock-names = "fck";
267 assigned-clocks = <&k3_clks 123 2>;
268 assigned-clock-parents = <&k3_clks 123 3>;
269 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>;
270 ti,timer-pwm;
271 /* Non-MPU Firmware usage */
275 mcu_timer8: timer@40480000 {
276 compatible = "ti,am654-timer";
280 clock-names = "fck";
281 assigned-clocks = <&k3_clks 124 2>;
282 assigned-clock-parents = <&k3_clks 124 3>;
283 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>;
284 ti,timer-pwm;
285 /* Non-MPU Firmware usage */
289 mcu_timer9: timer@40490000 {
290 compatible = "ti,am654-timer";
294 clock-names = "fck";
295 assigned-clocks = <&k3_clks 125 2>;
296 assigned-clock-parents = <&k3_clks 125 3>;
297 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
298 ti,timer-pwm;
299 /* Non-MPU Firmware usage */
304 compatible = "ti,j721e-uart", "ti,am654-uart";
307 current-speed = <115200>;
309 clock-names = "fclk";
310 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
315 compatible = "ti,j721e-uart", "ti,am654-uart";
318 current-speed = <115200>;
320 clock-names = "fclk";
321 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
326 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-parent = <&wkup_gpio_intr>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
335 ti,davinci-gpio-unbanked = <0>;
336 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
338 clock-names = "gpio";
343 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-parent = <&wkup_gpio_intr>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
352 ti,davinci-gpio-unbanked = <0>;
353 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
355 clock-names = "gpio";
360 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
363 #address-cells = <1>;
364 #size-cells = <0>;
366 clock-names = "fck";
367 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
372 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
375 #address-cells = <1>;
376 #size-cells = <0>;
378 clock-names = "fck";
379 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
384 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
387 #address-cells = <1>;
388 #size-cells = <0>;
390 clock-names = "fck";
391 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
399 reg-names = "m_can", "message_ram";
400 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
402 clock-names = "hclk", "cclk";
405 interrupt-names = "int0", "int1";
406 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
414 reg-names = "m_can", "message_ram";
415 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
417 clock-names = "hclk", "cclk";
420 interrupt-names = "int0", "int1";
421 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
426 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>;
437 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
440 #address-cells = <1>;
441 #size-cells = <0>;
442 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>;
448 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
451 #address-cells = <1>;
452 #size-cells = <0>;
453 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>;
459 bootph-all;
460 compatible = "simple-bus";
461 #address-cells = <2>;
462 #size-cells = <2>;
464 ti,sci-dev-id = <323>;
465 dma-coherent;
466 dma-ranges;
469 bootph-all;
470 compatible = "ti,am654-navss-ringacc";
476 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
477 ti,num-rings = <286>;
478 ti,sci-rm-range-gp-rings = <0x1>;
480 ti,sci-dev-id = <328>;
481 msi-parent = <&main_udmass_inta>;
484 mcu_udmap: dma-controller@285c0000 {
485 bootph-all;
486 compatible = "ti,j721e-navss-mcu-udmap";
493 reg-names = "gcfg", "rchanrt", "tchanrt",
495 msi-parent = <&main_udmass_inta>;
496 #dma-cells = <1>;
499 ti,sci-dev-id = <329>;
501 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
503 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
505 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
510 compatible = "ti,am654-secure-proxy";
511 #mbox-cells = <1>;
512 reg-names = "target_data", "rt", "scfg";
519 * firmware on non-MPU processors
525 compatible = "ti,j721e-cpsw-nuss";
526 #address-cells = <2>;
527 #size-cells = <2>;
529 reg-names = "cpsw_nuss";
531 dma-coherent;
533 clock-names = "fck";
534 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
545 dma-names = "tx0", "tx1", "tx2", "tx3",
550 ethernet-ports {
551 #address-cells = <1>;
552 #size-cells = <0>;
556 ti,mac-only;
558 ti,syscon-efuse = <&mcu_conf 0x200>;
564 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
566 #address-cells = <1>;
567 #size-cells = <0>;
569 clock-names = "fck";
574 compatible = "ti,am65-cpts";
577 clock-names = "cpts";
578 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
579 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
580 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "cpts";
582 ti,cpts-ext-ts-inputs = <4>;
583 ti,cpts-periodic-outputs = <2>;
588 compatible = "ti,j721s2-r5fss";
589 ti,cluster-mode = <1>;
590 #address-cells = <1>;
591 #size-cells = <1>;
594 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
597 compatible = "ti,j721s2-r5f";
600 reg-names = "atcm", "btcm";
602 ti,sci-dev-id = <346>;
603 ti,sci-proc-ids = <0x01 0xff>;
605 firmware-name = "j784s4-mcu-r5f0_0-fw";
606 ti,atcm-enable = <1>;
607 ti,btcm-enable = <1>;
612 compatible = "ti,j721s2-r5f";
615 reg-names = "atcm", "btcm";
617 ti,sci-dev-id = <347>;
618 ti,sci-proc-ids = <0x02 0xff>;
620 firmware-name = "j784s4-mcu-r5f0_1-fw";
621 ti,atcm-enable = <1>;
622 ti,btcm-enable = <1>;
627 wkup_vtm0: temperature-sensor@42040000 {
628 compatible = "ti,j7200-vtm";
631 power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
632 #thermal-sensor-cells = <1>;
636 compatible = "ti,am3359-tscadc";
639 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
641 assigned-clocks = <&k3_clks 0 2>;
642 assigned-clock-rates = <60000000>;
643 clock-names = "fck";
646 dma-names = "fifo0", "fifo1";
650 #io-channel-cells = <1>;
651 compatible = "ti,am3359-adc";
656 compatible = "ti,am3359-tscadc";
659 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
661 assigned-clocks = <&k3_clks 1 2>;
662 assigned-clock-rates = <60000000>;
663 clock-names = "fck";
666 dma-names = "fifo0", "fifo1";
670 #io-channel-cells = <1>;
671 compatible = "ti,am3359-adc";
676 compatible = "simple-bus";
678 #address-cells = <2>;
679 #size-cells = <2>;
683 compatible = "ti,am654-ospi", "cdns,qspi-nor";
687 cdns,fifo-depth = <256>;
688 cdns,fifo-width = <4>;
689 cdns,trigger-address = <0x0>;
691 assigned-clocks = <&k3_clks 161 7>;
692 assigned-clock-parents = <&k3_clks 161 9>;
693 assigned-clock-rates = <166666666>;
694 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
695 #address-cells = <1>;
696 #size-cells = <0>;
701 compatible = "ti,am654-ospi", "cdns,qspi-nor";
705 cdns,fifo-depth = <256>;
706 cdns,fifo-width = <4>;
707 cdns,trigger-address = <0x0>;
709 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
710 #address-cells = <1>;
711 #size-cells = <0>;
717 compatible = "ti,j721e-esm";
719 ti,esm-pins = <95>;
720 bootph-pre-ram;
724 compatible = "ti,j721e-esm";
726 ti,esm-pins = <63>;
727 bootph-pre-ram;
735 compatible = "ti,j7-rti-wdt";
738 power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>;
739 assigned-clocks = <&k3_clks 367 0>;
740 assigned-clock-parents = <&k3_clks 367 4>;
746 compatible = "ti,j7-rti-wdt";
749 power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>;
750 assigned-clocks = <&k3_clks 368 0>;
751 assigned-clock-parents = <&k3_clks 368 4>;