Lines Matching +full:0 +full:x44083000
20 reg = <0x00 0x44083000 0x00 0x1000>;
46 ranges = <0x0 0x00 0x43000000 0x20000>;
51 reg = <0x14 0x4>;
59 reg = <0x00 0x43600000 0x00 0x10000>,
60 <0x00 0x44880000 0x00 0x20000>,
61 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
84 pinctrl-single,function-mask = <0xffffffff>;
89 /* Proxy 0 addressing */
90 reg = <0x00 0x4301c038 0x00 0x02c>;
93 pinctrl-single,function-mask = <0xffffffff>;
98 /* Proxy 0 addressing */
99 reg = <0x00 0x4301c068 0x00 0x120>;
102 pinctrl-single,function-mask = <0xffffffff>;
107 /* Proxy 0 addressing */
108 reg = <0x00 0x4301c190 0x00 0x004>;
111 pinctrl-single,function-mask = <0xffffffff>;
116 reg = <0x00 0x42200000 0x00 0x400>;
129 reg = <0x00 0x40f04200 0x00 0x28>;
132 pinctrl-single,function-mask = <0x0000000f>;
140 reg = <0x00 0x40f04280 0x00 0x28>;
143 pinctrl-single,function-mask = <0x0000000f>;
150 reg = <0x00 0x40f00000 0x00 0x20000>;
153 ranges = <0x00 0x00 0x40f00000 0x20000>;
157 reg = <0x4040 0x4>;
164 reg = <0x00 0x40400000 0x00 0x400>;
179 reg = <0x00 0x40410000 0x00 0x400>;
193 reg = <0x00 0x40420000 0x00 0x400>;
207 reg = <0x00 0x40430000 0x00 0x400>;
221 reg = <0x00 0x40440000 0x00 0x400>;
235 reg = <0x00 0x40450000 0x00 0x400>;
249 reg = <0x00 0x40460000 0x00 0x400>;
263 reg = <0x00 0x40470000 0x00 0x400>;
277 reg = <0x00 0x40480000 0x00 0x400>;
291 reg = <0x00 0x40490000 0x00 0x400>;
305 reg = <0x00 0x42300000 0x00 0x200>;
308 clocks = <&k3_clks 397 0>;
316 reg = <0x00 0x40a00000 0x00 0x200>;
319 clocks = <&k3_clks 149 0>;
327 reg = <0x00 0x42110000 0x00 0x100>;
335 ti,davinci-gpio-unbanked = <0>;
337 clocks = <&k3_clks 167 0>;
344 reg = <0x00 0x42100000 0x00 0x100>;
352 ti,davinci-gpio-unbanked = <0>;
354 clocks = <&k3_clks 168 0>;
361 reg = <0x00 0x42120000 0x00 0x100>;
364 #size-cells = <0>;
373 reg = <0x00 0x40b00000 0x00 0x100>;
376 #size-cells = <0>;
385 reg = <0x00 0x40b10000 0x00 0x100>;
388 #size-cells = <0>;
397 reg = <0x00 0x40528000 0x00 0x200>,
398 <0x00 0x40500000 0x00 0x8000>;
406 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
412 reg = <0x00 0x40568000 0x00 0x200>,
413 <0x00 0x40540000 0x00 0x8000>;
421 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
427 reg = <0x00 0x040300000 0x00 0x400>;
430 #size-cells = <0>;
432 clocks = <&k3_clks 384 0>;
438 reg = <0x00 0x040310000 0x00 0x400>;
441 #size-cells = <0>;
443 clocks = <&k3_clks 385 0>;
449 reg = <0x00 0x040320000 0x00 0x400>;
452 #size-cells = <0>;
454 clocks = <&k3_clks 386 0>;
463 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
471 reg = <0x00 0x2b800000 0x00 0x400000>,
472 <0x00 0x2b000000 0x00 0x400000>,
473 <0x00 0x28590000 0x00 0x100>,
474 <0x00 0x2a500000 0x00 0x40000>,
475 <0x00 0x28440000 0x00 0x40000>;
478 ti,sci-rm-range-gp-rings = <0x1>;
487 reg = <0x00 0x285c0000 0x00 0x100>,
488 <0x00 0x2a800000 0x00 0x40000>,
489 <0x00 0x2aa00000 0x00 0x40000>,
490 <0x00 0x284a0000 0x00 0x4000>,
491 <0x00 0x284c0000 0x00 0x4000>,
492 <0x00 0x28400000 0x00 0x2000>;
501 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
502 <0x0f>; /* TX_HCHAN */
503 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
504 <0x0b>; /* RX_HCHAN */
505 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
513 reg = <0x00 0x2a480000 0x00 0x80000>,
514 <0x00 0x2a380000 0x00 0x80000>,
515 <0x00 0x2a400000 0x00 0x80000>;
528 reg = <0x00 0x46000000 0x00 0x200000>;
530 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
532 clocks = <&k3_clks 63 0>;
536 dmas = <&mcu_udmap 0xf000>,
537 <&mcu_udmap 0xf001>,
538 <&mcu_udmap 0xf002>,
539 <&mcu_udmap 0xf003>,
540 <&mcu_udmap 0xf004>,
541 <&mcu_udmap 0xf005>,
542 <&mcu_udmap 0xf006>,
543 <&mcu_udmap 0xf007>,
544 <&mcu_udmap 0x7000>;
552 #size-cells = <0>;
558 ti,syscon-efuse = <&mcu_conf 0x200>;
565 reg = <0x00 0xf00 0x00 0x100>;
567 #size-cells = <0>;
568 clocks = <&k3_clks 63 0>;
575 reg = <0x00 0x3d000 0x00 0x400>;
592 ranges = <0x41000000 0x00 0x41000000 0x20000>,
593 <0x41400000 0x00 0x41400000 0x20000>;
598 reg = <0x41000000 0x00010000>,
599 <0x41010000 0x00010000>;
603 ti,sci-proc-ids = <0x01 0xff>;
613 reg = <0x41400000 0x00010000>,
614 <0x41410000 0x00010000>;
618 ti,sci-proc-ids = <0x02 0xff>;
629 reg = <0x00 0x42040000 0x00 0x350>,
630 <0x00 0x42050000 0x00 0x350>;
637 reg = <0x00 0x40200000 0x00 0x1000>;
639 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
640 clocks = <&k3_clks 0 0>;
641 assigned-clocks = <&k3_clks 0 2>;
644 dmas = <&main_udmap 0x7400>,
645 <&main_udmap 0x7401>;
657 reg = <0x00 0x40210000 0x00 0x1000>;
660 clocks = <&k3_clks 1 0>;
664 dmas = <&main_udmap 0x7402>,
665 <&main_udmap 0x7403>;
677 reg = <0x00 0x47000000 0x00 0x100>;
684 reg = <0x00 0x47040000 0x00 0x100>,
685 <0x05 0x0000000 0x01 0x0000000>;
689 cdns,trigger-address = <0x0>;
696 #size-cells = <0>;
702 reg = <0x00 0x47050000 0x00 0x100>,
703 <0x07 0x0000000 0x01 0x0000000>;
707 cdns,trigger-address = <0x0>;
711 #size-cells = <0>;
718 reg = <0x00 0x40800000 0x00 0x1000>;
725 reg = <0x00 0x42080000 0x00 0x1000>;
736 reg = <0x00 0x40600000 0x00 0x100>;
739 assigned-clocks = <&k3_clks 367 0>;
747 reg = <0x00 0x40610000 0x00 0x100>;
750 assigned-clocks = <&k3_clks 368 0>;