Lines Matching +full:0 +full:x33d00000

16 		#clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x00004080 0x30>;
55 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
56 <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
57 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
58 <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
59 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
60 <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
87 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
88 <0x00 0x01900000 0x00 0x100000>, /* GICR */
89 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
90 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
91 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
98 reg = <0x00 0x01820000 0x00 0x10000>;
99 socionext,synquacer-pre-its = <0x1000000 0x400000>;
107 reg = <0x00 0x00a00000 0x00 0x800>;
119 /* Proxy 0 addressing */
120 reg = <0x00 0x11c000 0x00 0x120>;
123 pinctrl-single,function-mask = <0xffffffff>;
129 reg = <0x00 0x104200 0x00 0x50>;
132 pinctrl-single,function-mask = <0x00000007>;
138 reg = <0x00 0x104280 0x00 0x20>;
141 pinctrl-single,function-mask = <0x0000001f>;
146 reg = <0x00 0x4e00000 0x00 0x1200>;
150 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
152 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
153 <&main_udmap 0x4a41>;
158 reg = <0x00 0x4e10000 0x00 0x7d>;
165 reg = <0x00 0x2400000 0x00 0x400>;
177 reg = <0x00 0x2410000 0x00 0x400>;
189 reg = <0x00 0x2420000 0x00 0x400>;
201 reg = <0x00 0x2430000 0x00 0x400>;
213 reg = <0x00 0x2440000 0x00 0x400>;
225 reg = <0x00 0x2450000 0x00 0x400>;
237 reg = <0x00 0x2460000 0x00 0x400>;
249 reg = <0x00 0x2470000 0x00 0x400>;
261 reg = <0x00 0x2480000 0x00 0x400>;
273 reg = <0x00 0x2490000 0x00 0x400>;
285 reg = <0x00 0x24a0000 0x00 0x400>;
297 reg = <0x00 0x24b0000 0x00 0x400>;
309 reg = <0x00 0x24c0000 0x00 0x400>;
321 reg = <0x00 0x24d0000 0x00 0x400>;
333 reg = <0x00 0x24e0000 0x00 0x400>;
345 reg = <0x00 0x24f0000 0x00 0x400>;
357 reg = <0x00 0x2500000 0x00 0x400>;
369 reg = <0x00 0x2510000 0x00 0x400>;
381 reg = <0x00 0x2520000 0x00 0x400>;
393 reg = <0x00 0x2530000 0x00 0x400>;
405 reg = <0x00 0x02800000 0x00 0x200>;
408 clocks = <&k3_clks 146 0>;
416 reg = <0x00 0x02810000 0x00 0x200>;
419 clocks = <&k3_clks 388 0>;
427 reg = <0x00 0x02820000 0x00 0x200>;
430 clocks = <&k3_clks 389 0>;
438 reg = <0x00 0x02830000 0x00 0x200>;
441 clocks = <&k3_clks 390 0>;
449 reg = <0x00 0x02840000 0x00 0x200>;
452 clocks = <&k3_clks 391 0>;
460 reg = <0x00 0x02850000 0x00 0x200>;
463 clocks = <&k3_clks 392 0>;
471 reg = <0x00 0x02860000 0x00 0x200>;
474 clocks = <&k3_clks 393 0>;
482 reg = <0x00 0x02870000 0x00 0x200>;
485 clocks = <&k3_clks 394 0>;
493 reg = <0x00 0x02880000 0x00 0x200>;
496 clocks = <&k3_clks 395 0>;
504 reg = <0x00 0x02890000 0x00 0x200>;
507 clocks = <&k3_clks 396 0>;
515 reg = <0x00 0x00600000 0x00 0x100>;
523 ti,davinci-gpio-unbanked = <0>;
525 clocks = <&k3_clks 163 0>;
532 reg = <0x00 0x00610000 0x00 0x100>;
540 ti,davinci-gpio-unbanked = <0>;
542 clocks = <&k3_clks 164 0>;
549 reg = <0x00 0x00620000 0x00 0x100>;
557 ti,davinci-gpio-unbanked = <0>;
559 clocks = <&k3_clks 165 0>;
566 reg = <0x00 0x00630000 0x00 0x100>;
574 ti,davinci-gpio-unbanked = <0>;
576 clocks = <&k3_clks 166 0>;
583 reg = <0x00 0x02000000 0x00 0x100>;
586 #size-cells = <0>;
595 reg = <0x00 0x02010000 0x00 0x100>;
598 #size-cells = <0>;
607 reg = <0x00 0x02020000 0x00 0x100>;
610 #size-cells = <0>;
619 reg = <0x00 0x02030000 0x00 0x100>;
622 #size-cells = <0>;
631 reg = <0x00 0x02040000 0x00 0x100>;
634 #size-cells = <0>;
643 reg = <0x00 0x02050000 0x00 0x100>;
646 #size-cells = <0>;
655 reg = <0x00 0x02060000 0x00 0x100>;
658 #size-cells = <0>;
667 reg = <0x00 0x04f80000 0x00 0x1000>,
668 <0x00 0x04f88000 0x00 0x400>;
676 ti,otap-del-sel-legacy = <0x0>;
677 ti,otap-del-sel-mmc-hs = <0x0>;
678 ti,otap-del-sel-ddr52 = <0x6>;
679 ti,otap-del-sel-hs200 = <0x8>;
680 ti,otap-del-sel-hs400 = <0x5>;
681 ti,itap-del-sel-legacy = <0x10>;
682 ti,itap-del-sel-mmc-hs = <0xa>;
683 ti,strobe-sel = <0x77>;
684 ti,clkbuf-sel = <0x7>;
685 ti,trm-icp = <0x8>;
695 reg = <0x00 0x04fb0000 0x00 0x1000>,
696 <0x00 0x04fb8000 0x00 0x400>;
704 ti,otap-del-sel-legacy = <0x0>;
705 ti,otap-del-sel-sd-hs = <0x0>;
706 ti,otap-del-sel-sdr12 = <0xf>;
707 ti,otap-del-sel-sdr25 = <0xf>;
708 ti,otap-del-sel-sdr50 = <0xc>;
709 ti,otap-del-sel-sdr104 = <0x5>;
710 ti,otap-del-sel-ddr50 = <0xc>;
711 ti,itap-del-sel-legacy = <0x0>;
712 ti,itap-del-sel-sd-hs = <0x0>;
713 ti,itap-del-sel-sdr12 = <0x0>;
714 ti,itap-del-sel-sdr25 = <0x0>;
715 ti,itap-del-sel-ddr50 = <0x2>;
716 ti,clkbuf-sel = <0x7>;
717 ti,trm-icp = <0x8>;
719 sdhci-caps-mask = <0x00000003 0x00000000>;
736 ranges = <0x5060000 0x00 0x5060000 0x10000>;
741 reg = <0x05060000 0x010000>;
743 resets = <&serdes_wiz0 0>;
755 #size-cells = <0>;
773 ranges = <0x05070000 0x00 0x05070000 0x10000>;
778 reg = <0x05070000 0x010000>;
780 resets = <&serdes_wiz1 0>;
792 #size-cells = <0>;
810 ranges = <0x05020000 0x00 0x05020000 0x10000>;
815 reg = <0x05020000 0x010000>;
817 resets = <&serdes_wiz2 0>;
829 #size-cells = <0>;
847 ranges = <0x05050000 0x00 0x05050000 0x10000>,
848 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
857 reg = <0x05050000 0x010000>,
858 <0x0a030a00 0x40>; /* DPTX PHY */
860 resets = <&serdes_wiz4 0>;
872 #size-cells = <0>;
883 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
890 reg = <0x00 0x310e0000 0x00 0x4000>;
897 ti,interrupt-ranges = <0 64 64>,
904 reg = <0x00 0x33d00000 0x00 0x100000>;
906 #interrupt-cells = <0>;
911 ti,interrupt-ranges = <0 0 256>;
920 reg = <0x00 0x32c00000 0x00 0x100000>,
921 <0x00 0x32400000 0x00 0x100000>,
922 <0x00 0x32800000 0x00 0x100000>;
929 reg = <0x00 0x30e00000 0x00 0x1000>;
935 reg = <0x00 0x31f80000 0x00 0x200>;
945 reg = <0x00 0x31f81000 0x00 0x200>;
955 reg = <0x00 0x31f82000 0x00 0x200>;
965 reg = <0x00 0x31f83000 0x00 0x200>;
975 reg = <0x00 0x31f84000 0x00 0x200>;
985 reg = <0x00 0x31f85000 0x00 0x200>;
995 reg = <0x00 0x31f86000 0x00 0x200>;
1005 reg = <0x00 0x31f87000 0x00 0x200>;
1015 reg = <0x00 0x31f88000 0x00 0x200>;
1025 reg = <0x00 0x31f89000 0x00 0x200>;
1035 reg = <0x00 0x31f8a000 0x00 0x200>;
1045 reg = <0x00 0x31f8b000 0x00 0x200>;
1055 reg = <0x00 0x31f90000 0x00 0x200>;
1065 reg = <0x00 0x31f91000 0x00 0x200>;
1075 reg = <0x00 0x31f92000 0x00 0x200>;
1085 reg = <0x00 0x31f93000 0x00 0x200>;
1095 reg = <0x00 0x31f94000 0x00 0x200>;
1105 reg = <0x00 0x31f95000 0x00 0x200>;
1115 reg = <0x00 0x31f96000 0x00 0x200>;
1125 reg = <0x00 0x31f97000 0x00 0x200>;
1135 reg = <0x00 0x31f98000 0x00 0x200>;
1145 reg = <0x00 0x31f99000 0x00 0x200>;
1155 reg = <0x00 0x31f9a000 0x00 0x200>;
1165 reg = <0x00 0x31f9b000 0x00 0x200>;
1175 reg = <0x00 0x3c000000 0x00 0x400000>,
1176 <0x00 0x38000000 0x00 0x400000>,
1177 <0x00 0x31120000 0x00 0x100>,
1178 <0x00 0x33000000 0x00 0x40000>,
1179 <0x00 0x31080000 0x00 0x40000>;
1182 ti,sci-rm-range-gp-rings = <0x1>;
1190 reg = <0x00 0x31150000 0x00 0x100>,
1191 <0x00 0x34000000 0x00 0x80000>,
1192 <0x00 0x35000000 0x00 0x200000>,
1193 <0x00 0x30b00000 0x00 0x20000>,
1194 <0x00 0x30c00000 0x00 0x8000>,
1195 <0x00 0x30d00000 0x00 0x4000>;
1205 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1206 <0x0f>, /* TX_HCHAN */
1207 <0x10>; /* TX_UHCHAN */
1208 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1209 <0x0b>, /* RX_HCHAN */
1210 <0x0c>; /* RX_UHCHAN */
1211 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1216 reg = <0x00 0x311a0000 0x00 0x100>,
1217 <0x00 0x35d00000 0x00 0x20000>,
1218 <0x00 0x35c00000 0x00 0x10000>,
1219 <0x00 0x35e00000 0x00 0x80000>;
1225 ti,sci-rm-range-rchan = <0x21>;
1226 ti,sci-rm-range-tchan = <0x22>;
1232 reg = <0x00 0x310d0000 0x00 0x400>;
1234 clocks = <&k3_clks 282 0>;
1247 reg = <0x00 0x02701000 0x00 0x200>,
1248 <0x00 0x02708000 0x00 0x8000>;
1256 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1262 reg = <0x00 0x02711000 0x00 0x200>,
1263 <0x00 0x02718000 0x00 0x8000>;
1271 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1277 reg = <0x00 0x02721000 0x00 0x200>,
1278 <0x00 0x02728000 0x00 0x8000>;
1286 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1292 reg = <0x00 0x02731000 0x00 0x200>,
1293 <0x00 0x02738000 0x00 0x8000>;
1301 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1307 reg = <0x00 0x02741000 0x00 0x200>,
1308 <0x00 0x02748000 0x00 0x8000>;
1316 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1322 reg = <0x00 0x02751000 0x00 0x200>,
1323 <0x00 0x02758000 0x00 0x8000>;
1331 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1337 reg = <0x00 0x02761000 0x00 0x200>,
1338 <0x00 0x02768000 0x00 0x8000>;
1346 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1352 reg = <0x00 0x02771000 0x00 0x200>,
1353 <0x00 0x02778000 0x00 0x8000>;
1361 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1367 reg = <0x00 0x02781000 0x00 0x200>,
1368 <0x00 0x02788000 0x00 0x8000>;
1376 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1382 reg = <0x00 0x02791000 0x00 0x200>,
1383 <0x00 0x02798000 0x00 0x8000>;
1391 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1397 reg = <0x00 0x027a1000 0x00 0x200>,
1398 <0x00 0x027a8000 0x00 0x8000>;
1406 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1412 reg = <0x00 0x027b1000 0x00 0x200>,
1413 <0x00 0x027b8000 0x00 0x8000>;
1421 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1427 reg = <0x00 0x027c1000 0x00 0x200>,
1428 <0x00 0x027c8000 0x00 0x8000>;
1436 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1442 reg = <0x00 0x027d1000 0x00 0x200>,
1443 <0x00 0x027d8000 0x00 0x8000>;
1451 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1457 reg = <0x00 0x02681000 0x00 0x200>,
1458 <0x00 0x02688000 0x00 0x8000>;
1466 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1472 reg = <0x00 0x02691000 0x00 0x200>,
1473 <0x00 0x02698000 0x00 0x8000>;
1481 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1487 reg = <0x00 0x026a1000 0x00 0x200>,
1488 <0x00 0x026a8000 0x00 0x8000>;
1496 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1502 reg = <0x00 0x026b1000 0x00 0x200>,
1503 <0x00 0x026b8000 0x00 0x8000>;
1511 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1517 reg = <0x00 0x02100000 0x00 0x400>;
1520 #size-cells = <0>;
1528 reg = <0x00 0x02110000 0x00 0x400>;
1531 #size-cells = <0>;
1539 reg = <0x00 0x02120000 0x00 0x400>;
1542 #size-cells = <0>;
1550 reg = <0x00 0x02130000 0x00 0x400>;
1553 #size-cells = <0>;
1561 reg = <0x00 0x02140000 0x00 0x400>;
1564 #size-cells = <0>;
1572 reg = <0x00 0x02150000 0x00 0x400>;
1575 #size-cells = <0>;
1583 reg = <0x00 0x02160000 0x00 0x400>;
1586 #size-cells = <0>;
1594 reg = <0x00 0x02170000 0x00 0x400>;
1597 #size-cells = <0>;
1605 reg = <0x00 0x4e80000 0x00 0x100>;
1617 reg = <0x00 0x4e84000 0x00 0x10000>;
1632 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1633 <0x5d00000 0x00 0x5d00000 0x20000>;
1638 reg = <0x5c00000 0x00010000>,
1639 <0x5c10000 0x00010000>;
1643 ti,sci-proc-ids = <0x06 0xff>;
1653 reg = <0x5d00000 0x00010000>,
1654 <0x5d10000 0x00010000>;
1658 ti,sci-proc-ids = <0x07 0xff>;
1672 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1673 <0x5f00000 0x00 0x5f00000 0x20000>;
1678 reg = <0x5e00000 0x00010000>,
1679 <0x5e10000 0x00010000>;
1683 ti,sci-proc-ids = <0x08 0xff>;
1693 reg = <0x5f00000 0x00010000>,
1694 <0x5f10000 0x00010000>;
1698 ti,sci-proc-ids = <0x09 0xff>;
1712 ranges = <0x5900000 0x00 0x5900000 0x20000>,
1713 <0x5a00000 0x00 0x5a00000 0x20000>;
1718 reg = <0x5900000 0x00010000>,
1719 <0x5910000 0x00010000>;
1723 ti,sci-proc-ids = <0x0a 0xff>;
1733 reg = <0x5a00000 0x00010000>,
1734 <0x5a10000 0x00010000>;
1738 ti,sci-proc-ids = <0x0b 0xff>;
1749 reg = <0x00 0x64800000 0x00 0x00080000>,
1750 <0x00 0x64e00000 0x00 0x0000c000>;
1754 ti,sci-proc-ids = <0x30 0xff>;
1762 reg = <0x00 0x65800000 0x00 0x00080000>,
1763 <0x00 0x65e00000 0x00 0x0000c000>;
1767 ti,sci-proc-ids = <0x31 0xff>;
1775 reg = <0x00 0x66800000 0x00 0x00080000>,
1776 <0x00 0x66e00000 0x00 0x0000c000>;
1780 ti,sci-proc-ids = <0x32 0xff>;
1788 reg = <0x00 0x67800000 0x00 0x00080000>,
1789 <0x00 0x67e00000 0x00 0x0000c000>;
1793 ti,sci-proc-ids = <0x33 0xff>;
1801 reg = <0x00 0x700000 0x00 0x1000>;
1809 reg = <0x00 0x2200000 0x00 0x100>;
1812 assigned-clocks = <&k3_clks 348 0>;
1818 reg = <0x00 0x2210000 0x00 0x100>;
1821 assigned-clocks = <&k3_clks 349 0>;
1827 reg = <0x00 0x2220000 0x00 0x100>;
1830 assigned-clocks = <&k3_clks 350 0>;
1836 reg = <0x00 0x2230000 0x00 0x100>;
1839 assigned-clocks = <&k3_clks 351 0>;
1845 reg = <0x00 0x2240000 0x00 0x100>;
1848 assigned-clocks = <&k3_clks 352 0>;
1854 reg = <0x00 0x2250000 0x00 0x100>;
1857 assigned-clocks = <&k3_clks 353 0>;
1863 reg = <0x00 0x2260000 0x00 0x100>;
1866 assigned-clocks = <&k3_clks 354 0>;
1872 reg = <0x00 0x2270000 0x00 0x100>;
1875 assigned-clocks = <&k3_clks 355 0>;
1886 reg = <0x00 0x22f0000 0x00 0x100>;
1889 assigned-clocks = <&k3_clks 360 0>;
1897 reg = <0x00 0x2300000 0x00 0x100>;
1900 assigned-clocks = <&k3_clks 356 0>;
1908 reg = <0x00 0x2310000 0x00 0x100>;
1911 assigned-clocks = <&k3_clks 357 0>;
1919 reg = <0x00 0x2320000 0x00 0x100>;
1922 assigned-clocks = <&k3_clks 358 0>;
1930 reg = <0x00 0x2330000 0x00 0x100>;
1933 assigned-clocks = <&k3_clks 359 0>;
1941 reg = <0x00 0x23c0000 0x00 0x100>;
1944 assigned-clocks = <&k3_clks 361 0>;
1952 reg = <0x00 0x23d0000 0x00 0x100>;
1955 assigned-clocks = <&k3_clks 362 0>;
1963 reg = <0x00 0x23e0000 0x00 0x100>;
1966 assigned-clocks = <&k3_clks 363 0>;
1974 reg = <0x00 0x23f0000 0x00 0x100>;
1977 assigned-clocks = <&k3_clks 364 0>;
1985 reg = <0x00 0x2540000 0x00 0x100>;
1988 assigned-clocks = <&k3_clks 365 0>;
1996 reg = <0x00 0x2550000 0x00 0x100>;
1999 assigned-clocks = <&k3_clks 366 0>;
2007 reg = <0x0 0xa000000 0x0 0x30a00>,
2008 <0x0 0x4f40000 0x0 0x20>;
2018 #size-cells = <0>;
2027 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
2028 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
2029 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
2030 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
2031 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
2032 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
2033 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
2034 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
2035 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
2036 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
2037 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
2038 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
2039 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
2040 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
2041 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
2042 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
2043 <0x00 0x04af0000 0x00 0x10000>; /* wb */
2050 clocks = <&k3_clks 218 0>,