Lines Matching +full:am654 +full:- +full:vtm
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
26 k3_clks: clock-controller {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
44 compatible = "ti,am654-chipid";
50 compatible = "ti,am654-secure-proxy";
51 #mbox-cells = <1>;
52 reg-names = "target_data", "rt", "scfg";
59 * firmware on non-MPU processors
65 compatible = "mmio-sram";
68 #address-cells = <1>;
69 #size-cells = <1>;
73 compatible = "pinctrl-single";
76 #pinctrl-cells = <1>;
77 pinctrl-single,register-width = <32>;
78 pinctrl-single,function-mask = <0xffffffff>;
82 compatible = "pinctrl-single";
85 #pinctrl-cells = <1>;
86 pinctrl-single,register-width = <32>;
87 pinctrl-single,function-mask = <0xffffffff>;
91 compatible = "pinctrl-single";
94 #pinctrl-cells = <1>;
95 pinctrl-single,register-width = <32>;
96 pinctrl-single,function-mask = <0xffffffff>;
100 compatible = "pinctrl-single";
103 #pinctrl-cells = <1>;
104 pinctrl-single,register-width = <32>;
105 pinctrl-single,function-mask = <0xffffffff>;
110 compatible = "pinctrl-single";
112 #pinctrl-cells = <1>;
113 pinctrl-single,register-width = <32>;
114 pinctrl-single,function-mask = <0x0000000f>;
115 /* Non-MPU Firmware usage */
121 compatible = "pinctrl-single";
123 #pinctrl-cells = <1>;
124 pinctrl-single,register-width = <32>;
125 pinctrl-single,function-mask = <0x0000000f>;
126 /* Non-MPU Firmware usage */
130 wkup_gpio_intr: interrupt-controller@42200000 {
131 compatible = "ti,sci-intr";
133 ti,intr-trigger-type = <1>;
134 interrupt-controller;
135 interrupt-parent = <&gic500>;
136 #interrupt-cells = <1>;
138 ti,sci-dev-id = <125>;
139 ti,interrupt-ranges = <16 960 16>;
143 compatible = "syscon", "simple-mfd";
145 #address-cells = <1>;
146 #size-cells = <1>;
150 compatible = "ti,am654-phy-gmii-sel";
152 #phy-cells = <1>;
158 compatible = "ti,am654-timer";
162 clock-names = "fck";
163 assigned-clocks = <&k3_clks 35 1>;
164 assigned-clock-parents = <&k3_clks 35 2>;
165 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
166 ti,timer-pwm;
167 /* Non-MPU Firmware usage */
172 compatible = "ti,am654-timer";
176 clock-names = "fck";
177 assigned-clocks = <&k3_clks 83 1>;
178 assigned-clock-parents = <&k3_clks 83 2>;
179 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
180 ti,timer-pwm;
181 /* Non-MPU Firmware usage */
186 compatible = "ti,am654-timer";
190 clock-names = "fck";
191 assigned-clocks = <&k3_clks 84 1>;
192 assigned-clock-parents = <&k3_clks 84 2>;
193 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
194 ti,timer-pwm;
195 /* Non-MPU Firmware usage */
200 compatible = "ti,am654-timer";
204 clock-names = "fck";
205 assigned-clocks = <&k3_clks 85 1>;
206 assigned-clock-parents = <&k3_clks 85 2>;
207 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
208 ti,timer-pwm;
209 /* Non-MPU Firmware usage */
214 compatible = "ti,am654-timer";
218 clock-names = "fck";
219 assigned-clocks = <&k3_clks 86 1>;
220 assigned-clock-parents = <&k3_clks 86 2>;
221 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
222 ti,timer-pwm;
223 /* Non-MPU Firmware usage */
228 compatible = "ti,am654-timer";
232 clock-names = "fck";
233 assigned-clocks = <&k3_clks 87 1>;
234 assigned-clock-parents = <&k3_clks 87 2>;
235 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
236 ti,timer-pwm;
237 /* Non-MPU Firmware usage */
242 compatible = "ti,am654-timer";
246 clock-names = "fck";
247 assigned-clocks = <&k3_clks 88 1>;
248 assigned-clock-parents = <&k3_clks 88 2>;
249 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
250 ti,timer-pwm;
251 /* Non-MPU Firmware usage */
256 compatible = "ti,am654-timer";
260 clock-names = "fck";
261 assigned-clocks = <&k3_clks 89 1>;
262 assigned-clock-parents = <&k3_clks 89 2>;
263 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
264 ti,timer-pwm;
265 /* Non-MPU Firmware usage */
270 compatible = "ti,am654-timer";
274 clock-names = "fck";
275 assigned-clocks = <&k3_clks 90 1>;
276 assigned-clock-parents = <&k3_clks 90 2>;
277 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
278 ti,timer-pwm;
279 /* Non-MPU Firmware usage */
284 compatible = "ti,am654-timer";
288 clock-names = "fck";
289 assigned-clocks = <&k3_clks 91 1>;
290 assigned-clock-parents = <&k3_clks 91 2>;
291 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
292 ti,timer-pwm;
293 /* Non-MPU Firmware usage */
298 compatible = "ti,j721e-uart", "ti,am654-uart";
301 current-speed = <115200>;
303 clock-names = "fclk";
304 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
309 compatible = "ti,j721e-uart", "ti,am654-uart";
312 current-speed = <115200>;
314 clock-names = "fclk";
315 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
320 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-parent = <&wkup_gpio_intr>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
329 ti,davinci-gpio-unbanked = <0>;
330 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
332 clock-names = "gpio";
337 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
339 gpio-controller;
340 #gpio-cells = <2>;
341 interrupt-parent = <&wkup_gpio_intr>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
346 ti,davinci-gpio-unbanked = <0>;
347 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
349 clock-names = "gpio";
354 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
357 #address-cells = <1>;
358 #size-cells = <0>;
360 clock-names = "fck";
361 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
366 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
369 #address-cells = <1>;
370 #size-cells = <0>;
372 clock-names = "fck";
373 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
378 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
381 #address-cells = <1>;
382 #size-cells = <0>;
384 clock-names = "fck";
385 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
393 reg-names = "m_can", "message_ram";
394 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
396 clock-names = "hclk", "cclk";
399 interrupt-names = "int0", "int1";
400 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
408 reg-names = "m_can", "message_ram";
409 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
411 clock-names = "hclk", "cclk";
414 interrupt-names = "int0", "int1";
415 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
420 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
423 #address-cells = <1>;
424 #size-cells = <0>;
425 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
431 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
434 #address-cells = <1>;
435 #size-cells = <0>;
436 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
442 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
453 compatible = "simple-bus";
454 #address-cells = <2>;
455 #size-cells = <2>;
457 dma-coherent;
458 dma-ranges;
460 ti,sci-dev-id = <267>;
463 compatible = "ti,am654-navss-ringacc";
469 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
470 ti,num-rings = <286>;
471 ti,sci-rm-range-gp-rings = <0x1>;
473 ti,sci-dev-id = <272>;
474 msi-parent = <&main_udmass_inta>;
477 mcu_udmap: dma-controller@285c0000 {
478 compatible = "ti,j721e-navss-mcu-udmap";
485 reg-names = "gcfg", "rchanrt", "tchanrt",
487 msi-parent = <&main_udmass_inta>;
488 #dma-cells = <1>;
491 ti,sci-dev-id = <273>;
493 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
495 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
497 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
502 compatible = "ti,am654-secure-proxy";
503 #mbox-cells = <1>;
504 reg-names = "target_data", "rt", "scfg";
511 * firmware on non-MPU processors
517 compatible = "ti,j721e-cpsw-nuss";
518 #address-cells = <2>;
519 #size-cells = <2>;
521 reg-names = "cpsw_nuss";
523 dma-coherent;
525 clock-names = "fck";
526 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
537 dma-names = "tx0", "tx1", "tx2", "tx3",
541 ethernet-ports {
542 #address-cells = <1>;
543 #size-cells = <0>;
547 ti,mac-only;
549 ti,syscon-efuse = <&mcu_conf 0x200>;
555 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
557 #address-cells = <1>;
558 #size-cells = <0>;
560 clock-names = "fck";
565 compatible = "ti,am65-cpts";
568 clock-names = "cpts";
569 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
570 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
571 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
572 interrupt-names = "cpts";
573 ti,cpts-ext-ts-inputs = <4>;
574 ti,cpts-periodic-outputs = <2>;
579 compatible = "ti,am3359-tscadc";
582 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
584 assigned-clocks = <&k3_clks 0 2>;
585 assigned-clock-rates = <60000000>;
586 clock-names = "fck";
589 dma-names = "fifo0", "fifo1";
593 #io-channel-cells = <1>;
594 compatible = "ti,am3359-adc";
599 compatible = "ti,am3359-tscadc";
602 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
604 assigned-clocks = <&k3_clks 1 2>;
605 assigned-clock-rates = <60000000>;
606 clock-names = "fck";
609 dma-names = "fifo0", "fifo1";
613 #io-channel-cells = <1>;
614 compatible = "ti,am3359-adc";
619 compatible = "simple-bus";
620 #address-cells = <2>;
621 #size-cells = <2>;
627 compatible = "ti,am654-ospi", "cdns,qspi-nor";
631 cdns,fifo-depth = <256>;
632 cdns,fifo-width = <4>;
633 cdns,trigger-address = <0x0>;
635 assigned-clocks = <&k3_clks 109 5>;
636 assigned-clock-parents = <&k3_clks 109 7>;
637 assigned-clock-rates = <166666666>;
638 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
639 #address-cells = <1>;
640 #size-cells = <0>;
646 compatible = "ti,am654-ospi", "cdns,qspi-nor";
650 cdns,fifo-depth = <256>;
651 cdns,fifo-width = <4>;
652 cdns,trigger-address = <0x0>;
654 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
655 #address-cells = <1>;
656 #size-cells = <0>;
662 wkup_vtm0: temperature-sensor@42040000 {
663 compatible = "ti,j7200-vtm";
666 power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
667 #thermal-sensor-cells = <1>;
671 compatible = "ti,j721s2-r5fss";
672 ti,cluster-mode = <1>;
673 #address-cells = <1>;
674 #size-cells = <1>;
677 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
680 compatible = "ti,j721s2-r5f";
683 reg-names = "atcm", "btcm";
685 ti,sci-dev-id = <284>;
686 ti,sci-proc-ids = <0x01 0xff>;
688 firmware-name = "j721s2-mcu-r5f0_0-fw";
689 ti,atcm-enable = <1>;
690 ti,btcm-enable = <1>;
695 compatible = "ti,j721s2-r5f";
698 reg-names = "atcm", "btcm";
700 ti,sci-dev-id = <285>;
701 ti,sci-proc-ids = <0x02 0xff>;
703 firmware-name = "j721s2-mcu-r5f0_1-fw";
704 ti,atcm-enable = <1>;
705 ti,btcm-enable = <1>;
711 compatible = "ti,j721e-esm";
713 ti,esm-pins = <95>;
714 bootph-pre-ram;
718 compatible = "ti,j721e-esm";
720 ti,esm-pins = <63>;
721 bootph-pre-ram;
729 compatible = "ti,j7-rti-wdt";
732 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
733 assigned-clocks = <&k3_clks 295 1>;
734 assigned-clock-parents = <&k3_clks 295 5>;
740 compatible = "ti,j7-rti-wdt";
743 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
744 assigned-clocks = <&k3_clks 296 1>;
745 assigned-clock-parents = <&k3_clks 296 5>;