Lines Matching +full:0 +full:x4040
19 reg = <0x00 0x44083000 0x00 0x1000>;
41 ranges = <0x0 0x00 0x43000000 0x20000>;
45 reg = <0x14 0x4>;
53 reg = <0x00 0x43600000 0x00 0x10000>,
54 <0x00 0x44880000 0x00 0x20000>,
55 <0x00 0x44860000 0x00 0x20000>;
66 reg = <0x00 0x41c00000 0x00 0x100000>;
67 ranges = <0x00 0x00 0x41c00000 0x100000>;
74 /* Proxy 0 addressing */
75 reg = <0x00 0x4301c000 0x00 0x034>;
78 pinctrl-single,function-mask = <0xffffffff>;
83 /* Proxy 0 addressing */
84 reg = <0x00 0x4301c038 0x00 0x02C>;
87 pinctrl-single,function-mask = <0xffffffff>;
92 /* Proxy 0 addressing */
93 reg = <0x00 0x4301c068 0x00 0x120>;
96 pinctrl-single,function-mask = <0xffffffff>;
101 /* Proxy 0 addressing */
102 reg = <0x00 0x4301c190 0x00 0x004>;
105 pinctrl-single,function-mask = <0xffffffff>;
111 reg = <0x00 0x40f04200 0x00 0x28>;
114 pinctrl-single,function-mask = <0x0000000f>;
122 reg = <0x00 0x40f04280 0x00 0x28>;
125 pinctrl-single,function-mask = <0x0000000f>;
132 reg = <0x00 0x42200000 0x00 0x400>;
144 reg = <0x0 0x40f00000 0x0 0x20000>;
147 ranges = <0x0 0x0 0x40f00000 0x20000>;
151 reg = <0x4040 0x4>;
159 reg = <0x00 0x40400000 0x00 0x400>;
173 reg = <0x00 0x40410000 0x00 0x400>;
187 reg = <0x00 0x40420000 0x00 0x400>;
201 reg = <0x00 0x40430000 0x00 0x400>;
215 reg = <0x00 0x40440000 0x00 0x400>;
229 reg = <0x00 0x40450000 0x00 0x400>;
243 reg = <0x00 0x40460000 0x00 0x400>;
257 reg = <0x00 0x40470000 0x00 0x400>;
271 reg = <0x00 0x40480000 0x00 0x400>;
285 reg = <0x00 0x40490000 0x00 0x400>;
299 reg = <0x00 0x42300000 0x00 0x200>;
310 reg = <0x00 0x40a00000 0x00 0x200>;
321 reg = <0x00 0x42110000 0x00 0x100>;
329 ti,davinci-gpio-unbanked = <0>;
331 clocks = <&k3_clks 115 0>;
338 reg = <0x00 0x42100000 0x00 0x100>;
346 ti,davinci-gpio-unbanked = <0>;
348 clocks = <&k3_clks 116 0>;
355 reg = <0x00 0x42120000 0x00 0x100>;
358 #size-cells = <0>;
367 reg = <0x00 0x40b00000 0x00 0x100>;
370 #size-cells = <0>;
379 reg = <0x00 0x40b10000 0x00 0x100>;
382 #size-cells = <0>;
391 reg = <0x00 0x40528000 0x00 0x200>,
392 <0x00 0x40500000 0x00 0x8000>;
395 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
400 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
406 reg = <0x00 0x40568000 0x00 0x200>,
407 <0x00 0x40540000 0x00 0x8000>;
410 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
415 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
421 reg = <0x00 0x040300000 0x00 0x400>;
424 #size-cells = <0>;
426 clocks = <&k3_clks 347 0>;
432 reg = <0x00 0x040310000 0x00 0x400>;
435 #size-cells = <0>;
437 clocks = <&k3_clks 348 0>;
443 reg = <0x00 0x040320000 0x00 0x400>;
446 #size-cells = <0>;
448 clocks = <&k3_clks 349 0>;
456 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
464 reg = <0x0 0x2b800000 0x0 0x400000>,
465 <0x0 0x2b000000 0x0 0x400000>,
466 <0x0 0x28590000 0x0 0x100>,
467 <0x0 0x2a500000 0x0 0x40000>,
468 <0x0 0x28440000 0x0 0x40000>;
471 ti,sci-rm-range-gp-rings = <0x1>;
479 reg = <0x0 0x285c0000 0x0 0x100>,
480 <0x0 0x2a800000 0x0 0x40000>,
481 <0x0 0x2aa00000 0x0 0x40000>,
482 <0x0 0x284a0000 0x0 0x4000>,
483 <0x0 0x284c0000 0x0 0x4000>,
484 <0x0 0x28400000 0x0 0x2000>;
493 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
494 <0x0f>; /* TX_HCHAN */
495 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
496 <0x0b>; /* RX_HCHAN */
497 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
505 reg = <0x00 0x2a480000 0x00 0x80000>,
506 <0x00 0x2a380000 0x00 0x80000>,
507 <0x00 0x2a400000 0x00 0x80000>;
520 reg = <0x0 0x46000000 0x0 0x200000>;
522 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
528 dmas = <&mcu_udmap 0xf000>,
529 <&mcu_udmap 0xf001>,
530 <&mcu_udmap 0xf002>,
531 <&mcu_udmap 0xf003>,
532 <&mcu_udmap 0xf004>,
533 <&mcu_udmap 0xf005>,
534 <&mcu_udmap 0xf006>,
535 <&mcu_udmap 0xf007>,
536 <&mcu_udmap 0x7000>;
543 #size-cells = <0>;
549 ti,syscon-efuse = <&mcu_conf 0x200>;
556 reg = <0x0 0xf00 0x0 0x100>;
558 #size-cells = <0>;
566 reg = <0x0 0x3d000 0x0 0x400>;
580 reg = <0x00 0x40200000 0x00 0x1000>;
582 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
583 clocks = <&k3_clks 0 0>;
584 assigned-clocks = <&k3_clks 0 2>;
587 dmas = <&main_udmap 0x7400>,
588 <&main_udmap 0x7401>;
600 reg = <0x00 0x40210000 0x00 0x1000>;
603 clocks = <&k3_clks 1 0>;
607 dmas = <&main_udmap 0x7402>,
608 <&main_udmap 0x7403>;
622 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
623 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
624 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
628 reg = <0x00 0x47040000 0x00 0x100>,
629 <0x05 0x00000000 0x01 0x00000000>;
633 cdns,trigger-address = <0x0>;
640 #size-cells = <0>;
647 reg = <0x00 0x47050000 0x00 0x100>,
648 <0x07 0x00000000 0x01 0x00000000>;
652 cdns,trigger-address = <0x0>;
656 #size-cells = <0>;
664 reg = <0x00 0x42040000 0x0 0x350>,
665 <0x00 0x42050000 0x0 0x350>;
675 ranges = <0x41000000 0x00 0x41000000 0x20000>,
676 <0x41400000 0x00 0x41400000 0x20000>;
681 reg = <0x41000000 0x00010000>,
682 <0x41010000 0x00010000>;
686 ti,sci-proc-ids = <0x01 0xff>;
696 reg = <0x41400000 0x00010000>,
697 <0x41410000 0x00010000>;
701 ti,sci-proc-ids = <0x02 0xff>;
712 reg = <0x00 0x40800000 0x00 0x1000>;
719 reg = <0x00 0x42080000 0x00 0x1000>;
730 reg = <0x00 0x40600000 0x00 0x100>;
741 reg = <0x00 0x40610000 0x00 0x100>;