Lines Matching +full:sdhci +full:- +full:caps
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
24 #size-cells = <1>;
27 atf-sram@0 {
31 tifs-sram@1f0000 {
35 l3cache-sram@200000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "mmio-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
55 compatible = "ti,am654-phy-gmii-sel";
57 #phy-cells = <1>;
60 serdes_ln_ctrl: mux-controller@80 {
61 compatible = "mmio-mux";
63 #mux-control-cells = <1>;
64 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
68 ehrpwm_tbclk: clock-controller@140 {
69 compatible = "ti,am654-ehrpwm-tbclk";
71 #clock-cells = <1>;
76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
77 #pwm-cells = <3>;
79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
81 clock-names = "tbclk", "fck";
86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
87 #pwm-cells = <3>;
89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
91 clock-names = "tbclk", "fck";
96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
97 #pwm-cells = <3>;
99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
101 clock-names = "tbclk", "fck";
106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
107 #pwm-cells = <3>;
109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
111 clock-names = "tbclk", "fck";
116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
117 #pwm-cells = <3>;
119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
121 clock-names = "tbclk", "fck";
126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
127 #pwm-cells = <3>;
129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
131 clock-names = "tbclk", "fck";
135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
140 #interrupt-cells = <3>;
141 interrupt-controller;
151 gic_its: msi-controller@1820000 {
152 compatible = "arm,gic-v3-its";
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
155 msi-controller;
156 #msi-cells = <1>;
160 main_gpio_intr: interrupt-controller@a00000 {
161 compatible = "ti,sci-intr";
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
168 ti,sci-dev-id = <148>;
169 ti,interrupt-ranges = <8 392 56>;
173 compatible = "pinctrl-single";
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <0xffffffff>;
183 compatible = "pinctrl-single";
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width = <32>;
187 pinctrl-single,function-mask = <0x00000007>;
192 compatible = "pinctrl-single";
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0x0000001f>;
200 compatible = "ti,j721e-sa2ul";
202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
203 #address-cells = <2>;
204 #size-cells = <2>;
209 dma-names = "tx", "rx1", "rx2";
212 compatible = "inside-secure,safexcel-eip76";
219 compatible = "ti,am654-timer";
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63 1>;
225 assigned-clock-parents = <&k3_clks 63 2>;
226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
227 ti,timer-pwm;
231 compatible = "ti,am654-timer";
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64 1>;
237 assigned-clock-parents = <&k3_clks 64 2>;
238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
239 ti,timer-pwm;
243 compatible = "ti,am654-timer";
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65 1>;
249 assigned-clock-parents = <&k3_clks 65 2>;
250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
251 ti,timer-pwm;
255 compatible = "ti,am654-timer";
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66 1>;
261 assigned-clock-parents = <&k3_clks 66 2>;
262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
263 ti,timer-pwm;
267 compatible = "ti,am654-timer";
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67 1>;
273 assigned-clock-parents = <&k3_clks 67 2>;
274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
279 compatible = "ti,am654-timer";
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68 1>;
285 assigned-clock-parents = <&k3_clks 68 2>;
286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
287 ti,timer-pwm;
291 compatible = "ti,am654-timer";
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69 1>;
297 assigned-clock-parents = <&k3_clks 69 2>;
298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
299 ti,timer-pwm;
303 compatible = "ti,am654-timer";
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70 1>;
309 assigned-clock-parents = <&k3_clks 70 2>;
310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
311 ti,timer-pwm;
315 compatible = "ti,am654-timer";
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71 1>;
321 assigned-clock-parents = <&k3_clks 71 2>;
322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
323 ti,timer-pwm;
327 compatible = "ti,am654-timer";
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72 1>;
333 assigned-clock-parents = <&k3_clks 72 2>;
334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
335 ti,timer-pwm;
339 compatible = "ti,am654-timer";
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73 1>;
345 assigned-clock-parents = <&k3_clks 73 2>;
346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
347 ti,timer-pwm;
351 compatible = "ti,am654-timer";
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74 1>;
357 assigned-clock-parents = <&k3_clks 74 2>;
358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
359 ti,timer-pwm;
363 compatible = "ti,am654-timer";
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75 1>;
369 assigned-clock-parents = <&k3_clks 75 2>;
370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
371 ti,timer-pwm;
375 compatible = "ti,am654-timer";
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76 1>;
381 assigned-clock-parents = <&k3_clks 76 2>;
382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
383 ti,timer-pwm;
387 compatible = "ti,am654-timer";
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77 1>;
393 assigned-clock-parents = <&k3_clks 77 2>;
394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
395 ti,timer-pwm;
399 compatible = "ti,am654-timer";
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78 1>;
405 assigned-clock-parents = <&k3_clks 78 2>;
406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
407 ti,timer-pwm;
411 compatible = "ti,am654-timer";
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79 1>;
417 assigned-clock-parents = <&k3_clks 79 2>;
418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
419 ti,timer-pwm;
423 compatible = "ti,am654-timer";
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80 1>;
429 assigned-clock-parents = <&k3_clks 80 2>;
430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
431 ti,timer-pwm;
435 compatible = "ti,am654-timer";
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81 1>;
441 assigned-clock-parents = <&k3_clks 81 2>;
442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
443 ti,timer-pwm;
447 compatible = "ti,am654-timer";
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82 1>;
453 assigned-clock-parents = <&k3_clks 82 2>;
454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
455 ti,timer-pwm;
459 compatible = "ti,j721e-uart", "ti,am654-uart";
462 current-speed = <115200>;
464 clock-names = "fclk";
465 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
470 compatible = "ti,j721e-uart", "ti,am654-uart";
473 current-speed = <115200>;
475 clock-names = "fclk";
476 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
481 compatible = "ti,j721e-uart", "ti,am654-uart";
484 current-speed = <115200>;
486 clock-names = "fclk";
487 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
492 compatible = "ti,j721e-uart", "ti,am654-uart";
495 current-speed = <115200>;
497 clock-names = "fclk";
498 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
503 compatible = "ti,j721e-uart", "ti,am654-uart";
506 current-speed = <115200>;
508 clock-names = "fclk";
509 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
514 compatible = "ti,j721e-uart", "ti,am654-uart";
517 current-speed = <115200>;
519 clock-names = "fclk";
520 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
525 compatible = "ti,j721e-uart", "ti,am654-uart";
528 current-speed = <115200>;
530 clock-names = "fclk";
531 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
536 compatible = "ti,j721e-uart", "ti,am654-uart";
539 current-speed = <115200>;
541 clock-names = "fclk";
542 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
547 compatible = "ti,j721e-uart", "ti,am654-uart";
550 current-speed = <115200>;
552 clock-names = "fclk";
553 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
558 compatible = "ti,j721e-uart", "ti,am654-uart";
561 current-speed = <115200>;
563 clock-names = "fclk";
564 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
569 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-parent = <&main_gpio_intr>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
578 ti,davinci-gpio-unbanked = <0>;
579 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
581 clock-names = "gpio";
586 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-parent = <&main_gpio_intr>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
595 ti,davinci-gpio-unbanked = <0>;
596 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
598 clock-names = "gpio";
603 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
605 gpio-controller;
606 #gpio-cells = <2>;
607 interrupt-parent = <&main_gpio_intr>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
612 ti,davinci-gpio-unbanked = <0>;
613 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
615 clock-names = "gpio";
620 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-parent = <&main_gpio_intr>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
629 ti,davinci-gpio-unbanked = <0>;
630 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
632 clock-names = "gpio";
637 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
640 #address-cells = <1>;
641 #size-cells = <0>;
643 clock-names = "fck";
644 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
648 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
651 #address-cells = <1>;
652 #size-cells = <0>;
654 clock-names = "fck";
655 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
660 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
663 #address-cells = <1>;
664 #size-cells = <0>;
666 clock-names = "fck";
667 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
672 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
675 #address-cells = <1>;
676 #size-cells = <0>;
678 clock-names = "fck";
679 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
684 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
687 #address-cells = <1>;
688 #size-cells = <0>;
690 clock-names = "fck";
691 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
696 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
699 #address-cells = <1>;
700 #size-cells = <0>;
702 clock-names = "fck";
703 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
708 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
711 #address-cells = <1>;
712 #size-cells = <0>;
714 clock-names = "fck";
715 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
720 compatible = "ti,j721e-sdhci-8bit";
724 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
726 clock-names = "clk_ahb", "clk_xin";
727 assigned-clocks = <&k3_clks 98 1>;
728 assigned-clock-parents = <&k3_clks 98 2>;
729 bus-width = <8>;
730 ti,otap-del-sel-legacy = <0x0>;
731 ti,otap-del-sel-mmc-hs = <0x0>;
732 ti,otap-del-sel-ddr52 = <0x6>;
733 ti,otap-del-sel-hs200 = <0x8>;
734 ti,otap-del-sel-hs400 = <0x5>;
735 ti,itap-del-sel-legacy = <0x10>;
736 ti,itap-del-sel-mmc-hs = <0xa>;
737 ti,strobe-sel = <0x77>;
738 ti,clkbuf-sel = <0x7>;
739 ti,trm-icp = <0x8>;
740 mmc-ddr-1_8v;
741 mmc-hs200-1_8v;
742 mmc-hs400-1_8v;
743 dma-coherent;
748 compatible = "ti,j721e-sdhci-4bit";
752 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
754 clock-names = "clk_ahb", "clk_xin";
755 assigned-clocks = <&k3_clks 99 1>;
756 assigned-clock-parents = <&k3_clks 99 2>;
757 bus-width = <4>;
758 ti,otap-del-sel-legacy = <0x0>;
759 ti,otap-del-sel-sd-hs = <0x0>;
760 ti,otap-del-sel-sdr12 = <0xf>;
761 ti,otap-del-sel-sdr25 = <0xf>;
762 ti,otap-del-sel-sdr50 = <0xc>;
763 ti,otap-del-sel-sdr104 = <0x5>;
764 ti,otap-del-sel-ddr50 = <0xc>;
765 ti,itap-del-sel-legacy = <0x0>;
766 ti,itap-del-sel-sd-hs = <0x0>;
767 ti,itap-del-sel-sdr12 = <0x0>;
768 ti,itap-del-sel-sdr25 = <0x0>;
769 ti,itap-del-sel-ddr50 = <0x2>;
770 ti,clkbuf-sel = <0x7>;
771 ti,trm-icp = <0x8>;
772 dma-coherent;
774 sdhci-caps-mask = <0x00000003 0x00000000>;
779 compatible = "simple-bus";
780 #address-cells = <2>;
781 #size-cells = <2>;
783 ti,sci-dev-id = <224>;
784 dma-coherent;
785 dma-ranges;
787 main_navss_intr: interrupt-controller@310e0000 {
788 compatible = "ti,sci-intr";
790 ti,intr-trigger-type = <4>;
791 interrupt-controller;
792 interrupt-parent = <&gic500>;
793 #interrupt-cells = <1>;
795 ti,sci-dev-id = <227>;
796 ti,interrupt-ranges = <0 64 64>,
801 main_udmass_inta: msi-controller@33d00000 {
802 compatible = "ti,sci-inta";
804 interrupt-controller;
805 #interrupt-cells = <0>;
806 interrupt-parent = <&main_navss_intr>;
807 msi-controller;
809 ti,sci-dev-id = <265>;
810 ti,interrupt-ranges = <0 0 256>;
811 ti,unmapped-event-sources = <&main_bcdma_csi>;
815 compatible = "ti,am654-secure-proxy";
816 #mbox-cells = <1>;
817 reg-names = "target_data", "rt", "scfg";
821 interrupt-names = "rx_011";
826 compatible = "ti,am654-hwspinlock";
828 #hwlock-cells = <1>;
832 compatible = "ti,am654-mailbox";
834 #mbox-cells = <1>;
835 ti,mbox-num-users = <4>;
836 ti,mbox-num-fifos = <16>;
837 interrupt-parent = <&main_navss_intr>;
842 compatible = "ti,am654-mailbox";
844 #mbox-cells = <1>;
845 ti,mbox-num-users = <4>;
846 ti,mbox-num-fifos = <16>;
847 interrupt-parent = <&main_navss_intr>;
852 compatible = "ti,am654-mailbox";
854 #mbox-cells = <1>;
855 ti,mbox-num-users = <4>;
856 ti,mbox-num-fifos = <16>;
857 interrupt-parent = <&main_navss_intr>;
862 compatible = "ti,am654-mailbox";
864 #mbox-cells = <1>;
865 ti,mbox-num-users = <4>;
866 ti,mbox-num-fifos = <16>;
867 interrupt-parent = <&main_navss_intr>;
872 compatible = "ti,am654-mailbox";
874 #mbox-cells = <1>;
875 ti,mbox-num-users = <4>;
876 ti,mbox-num-fifos = <16>;
877 interrupt-parent = <&main_navss_intr>;
882 compatible = "ti,am654-mailbox";
884 #mbox-cells = <1>;
885 ti,mbox-num-users = <4>;
886 ti,mbox-num-fifos = <16>;
887 interrupt-parent = <&main_navss_intr>;
892 compatible = "ti,am654-mailbox";
894 #mbox-cells = <1>;
895 ti,mbox-num-users = <4>;
896 ti,mbox-num-fifos = <16>;
897 interrupt-parent = <&main_navss_intr>;
902 compatible = "ti,am654-mailbox";
904 #mbox-cells = <1>;
905 ti,mbox-num-users = <4>;
906 ti,mbox-num-fifos = <16>;
907 interrupt-parent = <&main_navss_intr>;
912 compatible = "ti,am654-mailbox";
914 #mbox-cells = <1>;
915 ti,mbox-num-users = <4>;
916 ti,mbox-num-fifos = <16>;
917 interrupt-parent = <&main_navss_intr>;
922 compatible = "ti,am654-mailbox";
924 #mbox-cells = <1>;
925 ti,mbox-num-users = <4>;
926 ti,mbox-num-fifos = <16>;
927 interrupt-parent = <&main_navss_intr>;
932 compatible = "ti,am654-mailbox";
934 #mbox-cells = <1>;
935 ti,mbox-num-users = <4>;
936 ti,mbox-num-fifos = <16>;
937 interrupt-parent = <&main_navss_intr>;
942 compatible = "ti,am654-mailbox";
944 #mbox-cells = <1>;
945 ti,mbox-num-users = <4>;
946 ti,mbox-num-fifos = <16>;
947 interrupt-parent = <&main_navss_intr>;
952 compatible = "ti,am654-mailbox";
954 #mbox-cells = <1>;
955 ti,mbox-num-users = <4>;
956 ti,mbox-num-fifos = <16>;
957 interrupt-parent = <&main_navss_intr>;
962 compatible = "ti,am654-mailbox";
964 #mbox-cells = <1>;
965 ti,mbox-num-users = <4>;
966 ti,mbox-num-fifos = <16>;
967 interrupt-parent = <&main_navss_intr>;
972 compatible = "ti,am654-mailbox";
974 #mbox-cells = <1>;
975 ti,mbox-num-users = <4>;
976 ti,mbox-num-fifos = <16>;
977 interrupt-parent = <&main_navss_intr>;
982 compatible = "ti,am654-mailbox";
984 #mbox-cells = <1>;
985 ti,mbox-num-users = <4>;
986 ti,mbox-num-fifos = <16>;
987 interrupt-parent = <&main_navss_intr>;
992 compatible = "ti,am654-mailbox";
994 #mbox-cells = <1>;
995 ti,mbox-num-users = <4>;
996 ti,mbox-num-fifos = <16>;
997 interrupt-parent = <&main_navss_intr>;
1002 compatible = "ti,am654-mailbox";
1004 #mbox-cells = <1>;
1005 ti,mbox-num-users = <4>;
1006 ti,mbox-num-fifos = <16>;
1007 interrupt-parent = <&main_navss_intr>;
1012 compatible = "ti,am654-mailbox";
1014 #mbox-cells = <1>;
1015 ti,mbox-num-users = <4>;
1016 ti,mbox-num-fifos = <16>;
1017 interrupt-parent = <&main_navss_intr>;
1022 compatible = "ti,am654-mailbox";
1024 #mbox-cells = <1>;
1025 ti,mbox-num-users = <4>;
1026 ti,mbox-num-fifos = <16>;
1027 interrupt-parent = <&main_navss_intr>;
1032 compatible = "ti,am654-mailbox";
1034 #mbox-cells = <1>;
1035 ti,mbox-num-users = <4>;
1036 ti,mbox-num-fifos = <16>;
1037 interrupt-parent = <&main_navss_intr>;
1042 compatible = "ti,am654-mailbox";
1044 #mbox-cells = <1>;
1045 ti,mbox-num-users = <4>;
1046 ti,mbox-num-fifos = <16>;
1047 interrupt-parent = <&main_navss_intr>;
1052 compatible = "ti,am654-mailbox";
1054 #mbox-cells = <1>;
1055 ti,mbox-num-users = <4>;
1056 ti,mbox-num-fifos = <16>;
1057 interrupt-parent = <&main_navss_intr>;
1062 compatible = "ti,am654-mailbox";
1064 #mbox-cells = <1>;
1065 ti,mbox-num-users = <4>;
1066 ti,mbox-num-fifos = <16>;
1067 interrupt-parent = <&main_navss_intr>;
1072 compatible = "ti,am654-navss-ringacc";
1078 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1079 ti,num-rings = <1024>;
1080 ti,sci-rm-range-gp-rings = <0x1>;
1082 ti,sci-dev-id = <259>;
1083 msi-parent = <&main_udmass_inta>;
1086 main_udmap: dma-controller@31150000 {
1087 compatible = "ti,j721e-navss-main-udmap";
1094 reg-names = "gcfg", "rchanrt", "tchanrt",
1096 msi-parent = <&main_udmass_inta>;
1097 #dma-cells = <1>;
1100 ti,sci-dev-id = <263>;
1103 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1106 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1109 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1112 main_bcdma_csi: dma-controller@311a0000 {
1113 compatible = "ti,j721s2-dmss-bcdma-csi";
1118 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1119 msi-parent = <&main_udmass_inta>;
1120 #dma-cells = <3>;
1122 ti,sci-dev-id = <225>;
1123 ti,sci-rm-range-rchan = <0x21>;
1124 ti,sci-rm-range-tchan = <0x22>;
1129 compatible = "ti,j721e-cpts";
1131 reg-names = "cpts";
1133 clock-names = "cpts";
1134 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1135 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1136 interrupts-extended = <&main_navss_intr 391>;
1137 interrupt-names = "cpts";
1138 ti,cpts-periodic-outputs = <6>;
1139 ti,cpts-ext-ts-inputs = <8>;
1144 compatible = "ti,j721e-cpsw-nuss";
1146 reg-names = "cpsw_nuss";
1148 #address-cells = <2>;
1149 #size-cells = <2>;
1150 dma-coherent;
1152 clock-names = "fck";
1153 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1164 dma-names = "tx0", "tx1", "tx2", "tx3",
1170 ethernet-ports {
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1176 ti,mac-only;
1184 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1189 clock-names = "fck";
1195 compatible = "ti,am65-cpts";
1198 clock-names = "cpts";
1199 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1200 interrupt-names = "cpts";
1201 ti,cpts-ext-ts-inputs = <4>;
1202 ti,cpts-periodic-outputs = <2>;
1206 usbss0: cdns-usb@4104000 {
1207 compatible = "ti,j721e-usb";
1210 clock-names = "ref", "lpm";
1211 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1212 assigned-clock-parents = <&k3_clks 360 17>;
1213 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1214 #address-cells = <2>;
1215 #size-cells = <2>;
1217 dma-coherent;
1226 reg-names = "otg", "xhci", "dev";
1230 interrupt-names = "host", "peripheral", "otg";
1231 maximum-speed = "super-speed";
1237 compatible = "ti,j721s2-wiz-10g";
1238 #address-cells = <1>;
1239 #size-cells = <1>;
1240 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1242 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1243 num-lanes = <4>;
1244 #reset-cells = <1>;
1245 #clock-cells = <1>;
1248 assigned-clocks = <&k3_clks 365 3>;
1249 assigned-clock-parents = <&k3_clks 365 7>;
1252 compatible = "ti,j721e-serdes-10g";
1254 reg-names = "torrent_phy";
1256 reset-names = "torrent_reset";
1259 clock-names = "refclk", "phy_en_refclk";
1260 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1263 assigned-clock-parents = <&k3_clks 365 3>,
1266 #address-cells = <1>;
1267 #size-cells = <0>;
1268 #clock-cells = <1>;
1275 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1280 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1281 interrupt-names = "link_state";
1284 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1285 max-link-speed = <3>;
1286 num-lanes = <4>;
1287 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1289 clock-names = "fck";
1290 #address-cells = <3>;
1291 #size-cells = <2>;
1292 bus-range = <0x0 0xff>;
1293 vendor-id = <0x104c>;
1294 device-id = <0xb013>;
1295 msi-map = <0x0 &gic_its 0x0 0x10000>;
1296 dma-coherent;
1299 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1300 #interrupt-cells = <1>;
1301 interrupt-map-mask = <0 0 0 7>;
1302 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1309 pcie1_intc: interrupt-controller {
1310 interrupt-controller;
1311 #interrupt-cells = <1>;
1312 interrupt-parent = <&gic500>;
1321 reg-names = "m_can", "message_ram";
1322 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1324 clock-names = "hclk", "cclk";
1327 interrupt-names = "int0", "int1";
1328 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1336 reg-names = "m_can", "message_ram";
1337 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1339 clock-names = "hclk", "cclk";
1342 interrupt-names = "int0", "int1";
1343 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1351 reg-names = "m_can", "message_ram";
1352 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1354 clock-names = "hclk", "cclk";
1357 interrupt-names = "int0", "int1";
1358 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1366 reg-names = "m_can", "message_ram";
1367 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1369 clock-names = "hclk", "cclk";
1372 interrupt-names = "int0", "int1";
1373 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1381 reg-names = "m_can", "message_ram";
1382 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1384 clock-names = "hclk", "cclk";
1387 interrupt-names = "int0", "int1";
1388 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1396 reg-names = "m_can", "message_ram";
1397 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1399 clock-names = "hclk", "cclk";
1402 interrupt-names = "int0", "int1";
1403 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1411 reg-names = "m_can", "message_ram";
1412 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1414 clock-names = "hclk", "cclk";
1417 interrupt-names = "int0", "int1";
1418 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1426 reg-names = "m_can", "message_ram";
1427 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1429 clock-names = "hclk", "cclk";
1432 interrupt-names = "int0", "int1";
1433 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1441 reg-names = "m_can", "message_ram";
1442 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1444 clock-names = "hclk", "cclk";
1447 interrupt-names = "int0", "int1";
1448 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1456 reg-names = "m_can", "message_ram";
1457 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1459 clock-names = "hclk", "cclk";
1462 interrupt-names = "int0", "int1";
1463 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1471 reg-names = "m_can", "message_ram";
1472 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1474 clock-names = "hclk", "cclk";
1477 interrupt-names = "int0", "int1";
1478 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1486 reg-names = "m_can", "message_ram";
1487 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1489 clock-names = "hclk", "cclk";
1492 interrupt-names = "int0", "int1";
1493 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1501 reg-names = "m_can", "message_ram";
1502 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1504 clock-names = "hclk", "cclk";
1507 interrupt-names = "int0", "int1";
1508 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1516 reg-names = "m_can", "message_ram";
1517 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1519 clock-names = "hclk", "cclk";
1522 interrupt-names = "int0", "int1";
1523 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1531 reg-names = "m_can", "message_ram";
1532 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1534 clock-names = "hclk", "cclk";
1537 interrupt-names = "int0", "int1";
1538 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1546 reg-names = "m_can", "message_ram";
1547 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1549 clock-names = "hclk", "cclk";
1552 interrupt-names = "int0", "int1";
1553 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1561 reg-names = "m_can", "message_ram";
1562 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1564 clock-names = "hclk", "cclk";
1567 interrupt-names = "int0", "int1";
1568 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1576 reg-names = "m_can", "message_ram";
1577 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1579 clock-names = "hclk", "cclk";
1582 interrupt-names = "int0", "int1";
1583 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1588 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1599 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1610 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1621 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1632 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1637 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1643 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1654 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1665 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1676 compatible = "ti,j721e-dss";
1694 reg-names = "common_m", "common_s0",
1705 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1706 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1711 interrupt-names = "common_m",
1722 compatible = "ti,j721s2-r5fss";
1723 ti,cluster-mode = <1>;
1724 #address-cells = <1>;
1725 #size-cells = <1>;
1728 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1731 compatible = "ti,j721s2-r5f";
1734 reg-names = "atcm", "btcm";
1736 ti,sci-dev-id = <279>;
1737 ti,sci-proc-ids = <0x06 0xff>;
1739 firmware-name = "j721s2-main-r5f0_0-fw";
1740 ti,atcm-enable = <1>;
1741 ti,btcm-enable = <1>;
1746 compatible = "ti,j721s2-r5f";
1749 reg-names = "atcm", "btcm";
1751 ti,sci-dev-id = <280>;
1752 ti,sci-proc-ids = <0x07 0xff>;
1754 firmware-name = "j721s2-main-r5f0_1-fw";
1755 ti,atcm-enable = <1>;
1756 ti,btcm-enable = <1>;
1762 compatible = "ti,j721s2-r5fss";
1763 ti,cluster-mode = <1>;
1764 #address-cells = <1>;
1765 #size-cells = <1>;
1768 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1771 compatible = "ti,j721s2-r5f";
1774 reg-names = "atcm", "btcm";
1776 ti,sci-dev-id = <281>;
1777 ti,sci-proc-ids = <0x08 0xff>;
1779 firmware-name = "j721s2-main-r5f1_0-fw";
1780 ti,atcm-enable = <1>;
1781 ti,btcm-enable = <1>;
1786 compatible = "ti,j721s2-r5f";
1789 reg-names = "atcm", "btcm";
1791 ti,sci-dev-id = <282>;
1792 ti,sci-proc-ids = <0x09 0xff>;
1794 firmware-name = "j721s2-main-r5f1_1-fw";
1795 ti,atcm-enable = <1>;
1796 ti,btcm-enable = <1>;
1802 compatible = "ti,j721s2-c71-dsp";
1805 reg-names = "l2sram", "l1dram";
1807 ti,sci-dev-id = <8>;
1808 ti,sci-proc-ids = <0x30 0xff>;
1810 firmware-name = "j721s2-c71_0-fw";
1815 compatible = "ti,j721s2-c71-dsp";
1818 reg-names = "l2sram", "l1dram";
1820 ti,sci-dev-id = <11>;
1821 ti,sci-proc-ids = <0x31 0xff>;
1823 firmware-name = "j721s2-c71_1-fw";
1828 compatible = "ti,j721e-esm";
1830 ti,esm-pins = <688>, <689>;
1831 bootph-pre-ram;
1835 compatible = "ti,j7-rti-wdt";
1838 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1839 assigned-clocks = <&k3_clks 286 1>;
1840 assigned-clock-parents = <&k3_clks 286 5>;
1844 compatible = "ti,j7-rti-wdt";
1847 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
1848 assigned-clocks = <&k3_clks 287 1>;
1849 assigned-clock-parents = <&k3_clks 287 5>;
1858 compatible = "ti,j7-rti-wdt";
1861 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
1862 assigned-clocks = <&k3_clks 290 1>;
1863 assigned-clock-parents = <&k3_clks 290 5>;
1869 compatible = "ti,j7-rti-wdt";
1872 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1873 assigned-clocks = <&k3_clks 288 1>;
1874 assigned-clock-parents = <&k3_clks 288 5>;
1880 compatible = "ti,j7-rti-wdt";
1883 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1884 assigned-clocks = <&k3_clks 289 1>;
1885 assigned-clock-parents = <&k3_clks 289 5>;
1891 compatible = "ti,j7-rti-wdt";
1894 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
1895 assigned-clocks = <&k3_clks 291 1>;
1896 assigned-clock-parents = <&k3_clks 291 5>;
1902 compatible = "ti,j7-rti-wdt";
1905 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
1906 assigned-clocks = <&k3_clks 292 1>;
1907 assigned-clock-parents = <&k3_clks 292 5>;
1913 compatible = "ti,j7-rti-wdt";
1916 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
1917 assigned-clocks = <&k3_clks 293 1>;
1918 assigned-clock-parents = <&k3_clks 293 5>;
1924 compatible = "ti,j7-rti-wdt";
1927 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
1928 assigned-clocks = <&k3_clks 294 1>;
1929 assigned-clock-parents = <&k3_clks 294 5>;