Lines Matching +full:0 +full:x40410000
19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
55 ranges = <0x0 0x00 0x43000000 0x20000>;
59 reg = <0x14 0x4>;
65 /* Proxy 0 addressing */
66 reg = <0x00 0x4301c000 0x00 0x178>;
69 pinctrl-single,function-mask = <0xffffffff>;
75 reg = <0x00 0x40f04200 0x00 0x28>;
78 pinctrl-single,function-mask = <0x0000000f>;
86 reg = <0x00 0x40f04280 0x00 0x28>;
89 pinctrl-single,function-mask = <0x0000000f>;
96 reg = <0x00 0x41c00000 0x00 0x100000>;
97 ranges = <0x0 0x00 0x41c00000 0x100000>;
104 reg = <0x00 0x40400000 0x00 0x400>;
118 reg = <0x00 0x40410000 0x00 0x400>;
122 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
132 reg = <0x00 0x40420000 0x00 0x400>;
146 reg = <0x00 0x40430000 0x00 0x400>;
150 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
160 reg = <0x00 0x40440000 0x00 0x400>;
174 reg = <0x00 0x40450000 0x00 0x400>;
178 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
188 reg = <0x00 0x40460000 0x00 0x400>;
202 reg = <0x00 0x40470000 0x00 0x400>;
206 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
216 reg = <0x00 0x40480000 0x00 0x400>;
230 reg = <0x00 0x40490000 0x00 0x400>;
234 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
243 reg = <0x00 0x42300000 0x00 0x100>;
248 clocks = <&k3_clks 287 0>;
255 reg = <0x00 0x40a00000 0x00 0x100>;
260 clocks = <&k3_clks 149 0>;
267 reg = <0x00 0x42200000 0x00 0x400>;
279 reg = <0x0 0x42110000 0x0 0x100>;
287 ti,davinci-gpio-unbanked = <0>;
289 clocks = <&k3_clks 113 0>;
296 reg = <0x0 0x42100000 0x0 0x100>;
304 ti,davinci-gpio-unbanked = <0>;
306 clocks = <&k3_clks 114 0>;
313 reg = <0x0 0x40b00000 0x0 0x100>;
316 #size-cells = <0>;
318 clocks = <&k3_clks 194 0>;
325 reg = <0x0 0x40b10000 0x0 0x100>;
328 #size-cells = <0>;
330 clocks = <&k3_clks 195 0>;
337 reg = <0x0 0x42120000 0x0 0x100>;
340 #size-cells = <0>;
342 clocks = <&k3_clks 197 0>;
349 reg = <0x0 0x47000000 0x0 0x100>;
356 reg = <0x00 0x47000004 0x00 0x2>;
358 mux-reg-masks = <0x4 0x2>; /* HBMC select */
363 reg = <0x00 0x47034000 0x00 0x100>,
364 <0x05 0x00000000 0x01 0x0000000>;
366 clocks = <&k3_clks 102 0>;
371 mux-controls = <&hbmc_mux 0>;
377 reg = <0x0 0x47040000 0x0 0x100>,
378 <0x5 0x00000000 0x1 0x0000000>;
382 cdns,trigger-address = <0x0>;
383 clocks = <&k3_clks 103 0>;
384 assigned-clocks = <&k3_clks 103 0>;
389 #size-cells = <0>;
395 reg = <0x0 0x47050000 0x0 0x100>,
396 <0x7 0x00000000 0x1 0x00000000>;
400 cdns,trigger-address = <0x0>;
401 clocks = <&k3_clks 104 0>;
404 #size-cells = <0>;
411 reg = <0x0 0x40200000 0x0 0x1000>;
413 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
414 clocks = <&k3_clks 0 1>;
415 assigned-clocks = <&k3_clks 0 3>;
418 dmas = <&main_udmap 0x7400>,
419 <&main_udmap 0x7401>;
431 reg = <0x0 0x40210000 0x0 0x1000>;
438 dmas = <&main_udmap 0x7402>,
439 <&main_udmap 0x7403>;
453 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
461 reg = <0x0 0x2b800000 0x0 0x400000>,
462 <0x0 0x2b000000 0x0 0x400000>,
463 <0x0 0x28590000 0x0 0x100>,
464 <0x0 0x2a500000 0x0 0x40000>,
465 <0x0 0x28440000 0x0 0x40000>;
468 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
476 reg = <0x0 0x285c0000 0x0 0x100>,
477 <0x0 0x2a800000 0x0 0x40000>,
478 <0x0 0x2aa00000 0x0 0x40000>,
479 <0x0 0x284a0000 0x0 0x4000>,
480 <0x0 0x284c0000 0x0 0x4000>,
481 <0x0 0x28400000 0x0 0x2000>;
491 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
492 <0x0f>; /* TX_HCHAN */
493 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
494 <0x0b>; /* RX_HCHAN */
495 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
503 reg = <0x0 0x2a480000 0x0 0x80000>,
504 <0x0 0x2a380000 0x0 0x80000>,
505 <0x0 0x2a400000 0x0 0x80000>;
518 reg = <0x0 0x46000000 0x0 0x200000>;
520 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
526 dmas = <&mcu_udmap 0xf000>,
527 <&mcu_udmap 0xf001>,
528 <&mcu_udmap 0xf002>,
529 <&mcu_udmap 0xf003>,
530 <&mcu_udmap 0xf004>,
531 <&mcu_udmap 0xf005>,
532 <&mcu_udmap 0xf006>,
533 <&mcu_udmap 0xf007>,
534 <&mcu_udmap 0x7000>;
541 #size-cells = <0>;
547 ti,syscon-efuse = <&mcu_conf 0x200>;
554 reg = <0x0 0xf00 0x0 0x100>;
556 #size-cells = <0>;
564 reg = <0x0 0x3d000 0x0 0x400>;
579 ranges = <0x41000000 0x00 0x41000000 0x20000>,
580 <0x41400000 0x00 0x41400000 0x20000>;
585 reg = <0x41000000 0x00008000>,
586 <0x41010000 0x00008000>;
590 ti,sci-proc-ids = <0x01 0xff>;
600 reg = <0x41400000 0x00008000>,
601 <0x41410000 0x00008000>;
605 ti,sci-proc-ids = <0x02 0xff>;
616 reg = <0x00 0x40528000 0x00 0x200>,
617 <0x00 0x40500000 0x00 0x8000>;
620 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
625 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
631 reg = <0x00 0x40568000 0x00 0x200>,
632 <0x00 0x40540000 0x00 0x8000>;
635 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
640 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
646 reg = <0x00 0x040300000 0x00 0x400>;
649 #size-cells = <0>;
651 clocks = <&k3_clks 274 0>;
657 reg = <0x00 0x040310000 0x00 0x400>;
660 #size-cells = <0>;
662 clocks = <&k3_clks 275 0>;
668 reg = <0x00 0x040320000 0x00 0x400>;
671 #size-cells = <0>;
673 clocks = <&k3_clks 276 0>;
679 reg = <0x00 0x42040000 0x00 0x350>,
680 <0x00 0x42050000 0x00 0x350>,
681 <0x00 0x43000300 0x00 0x10>;
688 reg = <0x00 0x40800000 0x00 0x1000>;