Lines Matching +full:ti +full:- +full:pruss
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
20 cmn_refclk1: clock-cmnrefclk1 {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
29 compatible = "mmio-sram";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 atf-sram@0 {
40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 serdes_ln_ctrl: mux-controller@4080 {
48 compatible = "mmio-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
67 ti,qsgmii-main-ports = <2>, <2>;
69 #phy-cells = <1>;
72 usb_serdes_mux: mux-controller@4000 {
73 compatible = "mmio-mux";
74 #mux-control-cells = <1>;
75 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
79 ehrpwm_tbclk: clock-controller@4140 {
80 compatible = "ti,am654-ehrpwm-tbclk";
82 #clock-cells = <1>;
87 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
88 #pwm-cells = <3>;
90 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
92 clock-names = "tbclk", "fck";
97 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
98 #pwm-cells = <3>;
100 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
102 clock-names = "tbclk", "fck";
107 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
108 #pwm-cells = <3>;
110 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
112 clock-names = "tbclk", "fck";
117 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
118 #pwm-cells = <3>;
120 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
122 clock-names = "tbclk", "fck";
127 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
128 #pwm-cells = <3>;
130 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
132 clock-names = "tbclk", "fck";
137 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
138 #pwm-cells = <3>;
140 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
142 clock-names = "tbclk", "fck";
146 gic500: interrupt-controller@1800000 {
147 compatible = "arm,gic-v3";
148 #address-cells = <2>;
149 #size-cells = <2>;
151 #interrupt-cells = <3>;
152 interrupt-controller;
162 gic_its: msi-controller@1820000 {
163 compatible = "arm,gic-v3-its";
165 socionext,synquacer-pre-its = <0x1000000 0x400000>;
166 msi-controller;
167 #msi-cells = <1>;
171 main_gpio_intr: interrupt-controller@a00000 {
172 compatible = "ti,sci-intr";
174 ti,intr-trigger-type = <1>;
175 interrupt-controller;
176 interrupt-parent = <&gic500>;
177 #interrupt-cells = <1>;
178 ti,sci = <&dmsc>;
179 ti,sci-dev-id = <131>;
180 ti,interrupt-ranges = <8 392 56>;
184 compatible = "simple-bus";
185 #address-cells = <2>;
186 #size-cells = <2>;
188 dma-coherent;
189 dma-ranges;
191 ti,sci-dev-id = <199>;
193 main_navss_intr: interrupt-controller@310e0000 {
194 compatible = "ti,sci-intr";
196 ti,intr-trigger-type = <4>;
197 interrupt-controller;
198 interrupt-parent = <&gic500>;
199 #interrupt-cells = <1>;
200 ti,sci = <&dmsc>;
201 ti,sci-dev-id = <213>;
202 ti,interrupt-ranges = <0 64 64>,
207 main_udmass_inta: interrupt-controller@33d00000 {
208 compatible = "ti,sci-inta";
210 interrupt-controller;
211 interrupt-parent = <&main_navss_intr>;
212 msi-controller;
213 #interrupt-cells = <0>;
214 ti,sci = <&dmsc>;
215 ti,sci-dev-id = <209>;
216 ti,interrupt-ranges = <0 0 256>;
220 compatible = "ti,am654-secure-proxy";
221 #mbox-cells = <1>;
222 reg-names = "target_data", "rt", "scfg";
226 interrupt-names = "rx_011";
231 compatible = "arm,smmu-v3";
233 interrupt-parent = <&gic500>;
236 interrupt-names = "eventq", "gerror";
237 #iommu-cells = <1>;
241 compatible = "ti,am654-hwspinlock";
243 #hwlock-cells = <1>;
247 compatible = "ti,am654-mailbox";
249 #mbox-cells = <1>;
250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <16>;
252 interrupt-parent = <&main_navss_intr>;
257 compatible = "ti,am654-mailbox";
259 #mbox-cells = <1>;
260 ti,mbox-num-users = <4>;
261 ti,mbox-num-fifos = <16>;
262 interrupt-parent = <&main_navss_intr>;
267 compatible = "ti,am654-mailbox";
269 #mbox-cells = <1>;
270 ti,mbox-num-users = <4>;
271 ti,mbox-num-fifos = <16>;
272 interrupt-parent = <&main_navss_intr>;
277 compatible = "ti,am654-mailbox";
279 #mbox-cells = <1>;
280 ti,mbox-num-users = <4>;
281 ti,mbox-num-fifos = <16>;
282 interrupt-parent = <&main_navss_intr>;
287 compatible = "ti,am654-mailbox";
289 #mbox-cells = <1>;
290 ti,mbox-num-users = <4>;
291 ti,mbox-num-fifos = <16>;
292 interrupt-parent = <&main_navss_intr>;
297 compatible = "ti,am654-mailbox";
299 #mbox-cells = <1>;
300 ti,mbox-num-users = <4>;
301 ti,mbox-num-fifos = <16>;
302 interrupt-parent = <&main_navss_intr>;
307 compatible = "ti,am654-mailbox";
309 #mbox-cells = <1>;
310 ti,mbox-num-users = <4>;
311 ti,mbox-num-fifos = <16>;
312 interrupt-parent = <&main_navss_intr>;
317 compatible = "ti,am654-mailbox";
319 #mbox-cells = <1>;
320 ti,mbox-num-users = <4>;
321 ti,mbox-num-fifos = <16>;
322 interrupt-parent = <&main_navss_intr>;
327 compatible = "ti,am654-mailbox";
329 #mbox-cells = <1>;
330 ti,mbox-num-users = <4>;
331 ti,mbox-num-fifos = <16>;
332 interrupt-parent = <&main_navss_intr>;
337 compatible = "ti,am654-mailbox";
339 #mbox-cells = <1>;
340 ti,mbox-num-users = <4>;
341 ti,mbox-num-fifos = <16>;
342 interrupt-parent = <&main_navss_intr>;
347 compatible = "ti,am654-mailbox";
349 #mbox-cells = <1>;
350 ti,mbox-num-users = <4>;
351 ti,mbox-num-fifos = <16>;
352 interrupt-parent = <&main_navss_intr>;
357 compatible = "ti,am654-mailbox";
359 #mbox-cells = <1>;
360 ti,mbox-num-users = <4>;
361 ti,mbox-num-fifos = <16>;
362 interrupt-parent = <&main_navss_intr>;
367 compatible = "ti,am654-navss-ringacc";
373 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
374 ti,num-rings = <1024>;
375 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
376 ti,sci = <&dmsc>;
377 ti,sci-dev-id = <211>;
378 msi-parent = <&main_udmass_inta>;
381 main_udmap: dma-controller@31150000 {
382 compatible = "ti,j721e-navss-main-udmap";
389 reg-names = "gcfg", "rchanrt", "tchanrt",
391 msi-parent = <&main_udmass_inta>;
392 #dma-cells = <1>;
394 ti,sci = <&dmsc>;
395 ti,sci-dev-id = <212>;
396 ti,ringacc = <&main_ringacc>;
398 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
401 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
404 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
408 compatible = "ti,j721e-cpts";
410 reg-names = "cpts";
412 clock-names = "cpts";
413 interrupts-extended = <&main_navss_intr 391>;
414 interrupt-names = "cpts";
415 ti,cpts-periodic-outputs = <6>;
416 ti,cpts-ext-ts-inputs = <8>;
421 compatible = "ti,j721e-cpswxg-nuss";
422 #address-cells = <2>;
423 #size-cells = <2>;
425 reg-names = "cpsw_nuss";
428 clock-names = "fck";
429 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
440 dma-names = "tx0", "tx1", "tx2", "tx3",
446 ethernet-ports {
447 #address-cells = <1>;
448 #size-cells = <0>;
451 ti,mac-only;
458 ti,mac-only;
465 ti,mac-only;
472 ti,mac-only;
479 ti,mac-only;
486 ti,mac-only;
493 ti,mac-only;
500 ti,mac-only;
507 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
509 #address-cells = <1>;
510 #size-cells = <0>;
512 clock-names = "fck";
518 compatible = "ti,j721e-cpts";
521 clock-names = "cpts";
522 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
523 interrupt-names = "cpts";
524 ti,cpts-ext-ts-inputs = <4>;
525 ti,cpts-periodic-outputs = <2>;
530 compatible = "ti,j721e-sa2ul";
532 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
533 #address-cells = <2>;
534 #size-cells = <2>;
539 dma-names = "tx", "rx1", "rx2";
542 compatible = "inside-secure,safexcel-eip76";
549 compatible = "pinctrl-single";
552 #pinctrl-cells = <1>;
553 pinctrl-single,register-width = <32>;
554 pinctrl-single,function-mask = <0xffffffff>;
559 compatible = "pinctrl-single";
561 #pinctrl-cells = <1>;
562 pinctrl-single,register-width = <32>;
563 pinctrl-single,function-mask = <0x00000007>;
568 compatible = "pinctrl-single";
570 #pinctrl-cells = <1>;
571 pinctrl-single,register-width = <32>;
572 pinctrl-single,function-mask = <0x0000001f>;
576 compatible = "ti,j721e-wiz-16g";
577 #address-cells = <1>;
578 #size-cells = <1>;
579 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
581 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
582 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
583 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
584 num-lanes = <2>;
585 #reset-cells = <1>;
588 wiz0_pll0_refclk: pll0-refclk {
590 #clock-cells = <0>;
591 assigned-clocks = <&wiz0_pll0_refclk>;
592 assigned-clock-parents = <&k3_clks 292 11>;
595 wiz0_pll1_refclk: pll1-refclk {
597 #clock-cells = <0>;
598 assigned-clocks = <&wiz0_pll1_refclk>;
599 assigned-clock-parents = <&k3_clks 292 0>;
602 wiz0_refclk_dig: refclk-dig {
604 #clock-cells = <0>;
605 assigned-clocks = <&wiz0_refclk_dig>;
606 assigned-clock-parents = <&k3_clks 292 11>;
609 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
611 #clock-cells = <0>;
614 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
616 #clock-cells = <0>;
620 compatible = "ti,sierra-phy-t0";
621 reg-names = "serdes";
623 #address-cells = <1>;
624 #size-cells = <0>;
625 #clock-cells = <1>;
627 reset-names = "sierra_reset";
630 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
636 compatible = "ti,j721e-wiz-16g";
637 #address-cells = <1>;
638 #size-cells = <1>;
639 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
641 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
642 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
643 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
644 num-lanes = <2>;
645 #reset-cells = <1>;
648 wiz1_pll0_refclk: pll0-refclk {
650 #clock-cells = <0>;
651 assigned-clocks = <&wiz1_pll0_refclk>;
652 assigned-clock-parents = <&k3_clks 293 13>;
655 wiz1_pll1_refclk: pll1-refclk {
657 #clock-cells = <0>;
658 assigned-clocks = <&wiz1_pll1_refclk>;
659 assigned-clock-parents = <&k3_clks 293 0>;
662 wiz1_refclk_dig: refclk-dig {
664 #clock-cells = <0>;
665 assigned-clocks = <&wiz1_refclk_dig>;
666 assigned-clock-parents = <&k3_clks 293 13>;
669 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
671 #clock-cells = <0>;
674 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
676 #clock-cells = <0>;
680 compatible = "ti,sierra-phy-t0";
681 reg-names = "serdes";
683 #address-cells = <1>;
684 #size-cells = <0>;
685 #clock-cells = <1>;
687 reset-names = "sierra_reset";
690 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
696 compatible = "ti,j721e-wiz-16g";
697 #address-cells = <1>;
698 #size-cells = <1>;
699 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
701 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
702 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
703 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
704 num-lanes = <2>;
705 #reset-cells = <1>;
708 wiz2_pll0_refclk: pll0-refclk {
710 #clock-cells = <0>;
711 assigned-clocks = <&wiz2_pll0_refclk>;
712 assigned-clock-parents = <&k3_clks 294 11>;
715 wiz2_pll1_refclk: pll1-refclk {
717 #clock-cells = <0>;
718 assigned-clocks = <&wiz2_pll1_refclk>;
719 assigned-clock-parents = <&k3_clks 294 0>;
722 wiz2_refclk_dig: refclk-dig {
724 #clock-cells = <0>;
725 assigned-clocks = <&wiz2_refclk_dig>;
726 assigned-clock-parents = <&k3_clks 294 11>;
729 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
731 #clock-cells = <0>;
734 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
736 #clock-cells = <0>;
740 compatible = "ti,sierra-phy-t0";
741 reg-names = "serdes";
743 #address-cells = <1>;
744 #size-cells = <0>;
745 #clock-cells = <1>;
747 reset-names = "sierra_reset";
750 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
756 compatible = "ti,j721e-wiz-16g";
757 #address-cells = <1>;
758 #size-cells = <1>;
759 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
761 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
762 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
763 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
764 num-lanes = <2>;
765 #reset-cells = <1>;
768 wiz3_pll0_refclk: pll0-refclk {
770 #clock-cells = <0>;
771 assigned-clocks = <&wiz3_pll0_refclk>;
772 assigned-clock-parents = <&k3_clks 295 9>;
775 wiz3_pll1_refclk: pll1-refclk {
777 #clock-cells = <0>;
778 assigned-clocks = <&wiz3_pll1_refclk>;
779 assigned-clock-parents = <&k3_clks 295 0>;
782 wiz3_refclk_dig: refclk-dig {
784 #clock-cells = <0>;
785 assigned-clocks = <&wiz3_refclk_dig>;
786 assigned-clock-parents = <&k3_clks 295 9>;
789 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
791 #clock-cells = <0>;
794 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
796 #clock-cells = <0>;
800 compatible = "ti,sierra-phy-t0";
801 reg-names = "serdes";
803 #address-cells = <1>;
804 #size-cells = <0>;
805 #clock-cells = <1>;
807 reset-names = "sierra_reset";
810 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
816 compatible = "ti,j721e-pcie-host";
821 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
822 interrupt-names = "link_state";
825 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
826 max-link-speed = <3>;
827 num-lanes = <2>;
828 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
830 clock-names = "fck";
831 #address-cells = <3>;
832 #size-cells = <2>;
833 bus-range = <0x0 0xff>;
834 vendor-id = <0x104c>;
835 device-id = <0xb00d>;
836 msi-map = <0x0 &gic_its 0x0 0x10000>;
837 dma-coherent;
840 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
845 compatible = "ti,j721e-pcie-host";
850 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
851 interrupt-names = "link_state";
854 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
855 max-link-speed = <3>;
856 num-lanes = <2>;
857 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
859 clock-names = "fck";
860 #address-cells = <3>;
861 #size-cells = <2>;
862 bus-range = <0x0 0xff>;
863 vendor-id = <0x104c>;
864 device-id = <0xb00d>;
865 msi-map = <0x0 &gic_its 0x10000 0x10000>;
866 dma-coherent;
869 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
874 compatible = "ti,j721e-pcie-host";
879 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
880 interrupt-names = "link_state";
883 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
884 max-link-speed = <3>;
885 num-lanes = <2>;
886 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
888 clock-names = "fck";
889 #address-cells = <3>;
890 #size-cells = <2>;
891 bus-range = <0x0 0xff>;
892 vendor-id = <0x104c>;
893 device-id = <0xb00d>;
894 msi-map = <0x0 &gic_its 0x20000 0x10000>;
895 dma-coherent;
898 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
903 compatible = "ti,j721e-pcie-host";
908 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
909 interrupt-names = "link_state";
912 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
913 max-link-speed = <3>;
914 num-lanes = <2>;
915 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
917 clock-names = "fck";
918 #address-cells = <3>;
919 #size-cells = <2>;
920 bus-range = <0x0 0xff>;
921 vendor-id = <0x104c>;
922 device-id = <0xb00d>;
923 msi-map = <0x0 &gic_its 0x30000 0x10000>;
924 dma-coherent;
927 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
932 compatible = "ti,am64-wiz-10g";
933 #address-cells = <1>;
934 #size-cells = <1>;
935 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
937 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
938 assigned-clocks = <&k3_clks 297 9>;
939 assigned-clock-parents = <&k3_clks 297 10>;
940 assigned-clock-rates = <19200000>;
941 num-lanes = <4>;
942 #reset-cells = <1>;
943 #clock-cells = <1>;
952 compatible = "ti,j721e-serdes-10g";
955 reg-names = "torrent_phy", "dptx_phy";
958 reset-names = "torrent_reset";
960 clock-names = "refclk";
961 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
964 assigned-clock-parents = <&k3_clks 297 9>,
967 #address-cells = <1>;
968 #size-cells = <0>;
973 compatible = "ti,am654-timer";
977 clock-names = "fck";
978 assigned-clocks = <&k3_clks 49 1>;
979 assigned-clock-parents = <&k3_clks 49 2>;
980 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
981 ti,timer-pwm;
985 compatible = "ti,am654-timer";
989 clock-names = "fck";
990 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
991 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
992 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
993 ti,timer-pwm;
997 compatible = "ti,am654-timer";
1001 clock-names = "fck";
1002 assigned-clocks = <&k3_clks 51 1>;
1003 assigned-clock-parents = <&k3_clks 51 2>;
1004 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1005 ti,timer-pwm;
1009 compatible = "ti,am654-timer";
1013 clock-names = "fck";
1014 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1015 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1016 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1017 ti,timer-pwm;
1021 compatible = "ti,am654-timer";
1025 clock-names = "fck";
1026 assigned-clocks = <&k3_clks 53 1>;
1027 assigned-clock-parents = <&k3_clks 53 2>;
1028 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1029 ti,timer-pwm;
1033 compatible = "ti,am654-timer";
1037 clock-names = "fck";
1038 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1039 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1040 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1041 ti,timer-pwm;
1045 compatible = "ti,am654-timer";
1049 clock-names = "fck";
1050 assigned-clocks = <&k3_clks 55 1>;
1051 assigned-clock-parents = <&k3_clks 55 2>;
1052 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1053 ti,timer-pwm;
1057 compatible = "ti,am654-timer";
1061 clock-names = "fck";
1062 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1063 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1064 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1065 ti,timer-pwm;
1069 compatible = "ti,am654-timer";
1073 clock-names = "fck";
1074 assigned-clocks = <&k3_clks 58 1>;
1075 assigned-clock-parents = <&k3_clks 58 2>;
1076 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1077 ti,timer-pwm;
1081 compatible = "ti,am654-timer";
1085 clock-names = "fck";
1086 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1087 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1088 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1089 ti,timer-pwm;
1093 compatible = "ti,am654-timer";
1097 clock-names = "fck";
1098 assigned-clocks = <&k3_clks 60 1>;
1099 assigned-clock-parents = <&k3_clks 60 2>;
1100 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1101 ti,timer-pwm;
1105 compatible = "ti,am654-timer";
1109 clock-names = "fck";
1110 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1111 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1112 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1113 ti,timer-pwm;
1117 compatible = "ti,am654-timer";
1121 clock-names = "fck";
1122 assigned-clocks = <&k3_clks 63 1>;
1123 assigned-clock-parents = <&k3_clks 63 2>;
1124 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1125 ti,timer-pwm;
1129 compatible = "ti,am654-timer";
1133 clock-names = "fck";
1134 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1135 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1136 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1137 ti,timer-pwm;
1141 compatible = "ti,am654-timer";
1145 clock-names = "fck";
1146 assigned-clocks = <&k3_clks 65 1>;
1147 assigned-clock-parents = <&k3_clks 65 2>;
1148 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1149 ti,timer-pwm;
1153 compatible = "ti,am654-timer";
1157 clock-names = "fck";
1158 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1159 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1160 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1161 ti,timer-pwm;
1165 compatible = "ti,am654-timer";
1169 clock-names = "fck";
1170 assigned-clocks = <&k3_clks 67 1>;
1171 assigned-clock-parents = <&k3_clks 67 2>;
1172 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1173 ti,timer-pwm;
1177 compatible = "ti,am654-timer";
1181 clock-names = "fck";
1182 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1183 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1184 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1185 ti,timer-pwm;
1189 compatible = "ti,am654-timer";
1193 clock-names = "fck";
1194 assigned-clocks = <&k3_clks 69 1>;
1195 assigned-clock-parents = <&k3_clks 69 2>;
1196 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1197 ti,timer-pwm;
1201 compatible = "ti,am654-timer";
1205 clock-names = "fck";
1206 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1207 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1208 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1209 ti,timer-pwm;
1213 compatible = "ti,j721e-uart", "ti,am654-uart";
1216 clock-frequency = <48000000>;
1217 current-speed = <115200>;
1218 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1220 clock-names = "fclk";
1225 compatible = "ti,j721e-uart", "ti,am654-uart";
1228 clock-frequency = <48000000>;
1229 current-speed = <115200>;
1230 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1232 clock-names = "fclk";
1237 compatible = "ti,j721e-uart", "ti,am654-uart";
1240 clock-frequency = <48000000>;
1241 current-speed = <115200>;
1242 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1244 clock-names = "fclk";
1249 compatible = "ti,j721e-uart", "ti,am654-uart";
1252 clock-frequency = <48000000>;
1253 current-speed = <115200>;
1254 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1256 clock-names = "fclk";
1261 compatible = "ti,j721e-uart", "ti,am654-uart";
1264 clock-frequency = <48000000>;
1265 current-speed = <115200>;
1266 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1268 clock-names = "fclk";
1273 compatible = "ti,j721e-uart", "ti,am654-uart";
1276 clock-frequency = <48000000>;
1277 current-speed = <115200>;
1278 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1280 clock-names = "fclk";
1285 compatible = "ti,j721e-uart", "ti,am654-uart";
1288 clock-frequency = <48000000>;
1289 current-speed = <115200>;
1290 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1292 clock-names = "fclk";
1297 compatible = "ti,j721e-uart", "ti,am654-uart";
1300 clock-frequency = <48000000>;
1301 current-speed = <115200>;
1302 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1304 clock-names = "fclk";
1309 compatible = "ti,j721e-uart", "ti,am654-uart";
1312 clock-frequency = <48000000>;
1313 current-speed = <115200>;
1314 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1316 clock-names = "fclk";
1321 compatible = "ti,j721e-uart", "ti,am654-uart";
1324 clock-frequency = <48000000>;
1325 current-speed = <115200>;
1326 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1328 clock-names = "fclk";
1333 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1335 gpio-controller;
1336 #gpio-cells = <2>;
1337 interrupt-parent = <&main_gpio_intr>;
1340 interrupt-controller;
1341 #interrupt-cells = <2>;
1342 ti,ngpio = <128>;
1343 ti,davinci-gpio-unbanked = <0>;
1344 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1346 clock-names = "gpio";
1351 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1353 gpio-controller;
1354 #gpio-cells = <2>;
1355 interrupt-parent = <&main_gpio_intr>;
1357 interrupt-controller;
1358 #interrupt-cells = <2>;
1359 ti,ngpio = <36>;
1360 ti,davinci-gpio-unbanked = <0>;
1361 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1363 clock-names = "gpio";
1368 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1370 gpio-controller;
1371 #gpio-cells = <2>;
1372 interrupt-parent = <&main_gpio_intr>;
1375 interrupt-controller;
1376 #interrupt-cells = <2>;
1377 ti,ngpio = <128>;
1378 ti,davinci-gpio-unbanked = <0>;
1379 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1381 clock-names = "gpio";
1386 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1388 gpio-controller;
1389 #gpio-cells = <2>;
1390 interrupt-parent = <&main_gpio_intr>;
1392 interrupt-controller;
1393 #interrupt-cells = <2>;
1394 ti,ngpio = <36>;
1395 ti,davinci-gpio-unbanked = <0>;
1396 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1398 clock-names = "gpio";
1403 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1405 gpio-controller;
1406 #gpio-cells = <2>;
1407 interrupt-parent = <&main_gpio_intr>;
1410 interrupt-controller;
1411 #interrupt-cells = <2>;
1412 ti,ngpio = <128>;
1413 ti,davinci-gpio-unbanked = <0>;
1414 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1416 clock-names = "gpio";
1421 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1423 gpio-controller;
1424 #gpio-cells = <2>;
1425 interrupt-parent = <&main_gpio_intr>;
1427 interrupt-controller;
1428 #interrupt-cells = <2>;
1429 ti,ngpio = <36>;
1430 ti,davinci-gpio-unbanked = <0>;
1431 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1433 clock-names = "gpio";
1438 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1440 gpio-controller;
1441 #gpio-cells = <2>;
1442 interrupt-parent = <&main_gpio_intr>;
1445 interrupt-controller;
1446 #interrupt-cells = <2>;
1447 ti,ngpio = <128>;
1448 ti,davinci-gpio-unbanked = <0>;
1449 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1451 clock-names = "gpio";
1456 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1458 gpio-controller;
1459 #gpio-cells = <2>;
1460 interrupt-parent = <&main_gpio_intr>;
1462 interrupt-controller;
1463 #interrupt-cells = <2>;
1464 ti,ngpio = <36>;
1465 ti,davinci-gpio-unbanked = <0>;
1466 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1468 clock-names = "gpio";
1473 compatible = "ti,j721e-sdhci-8bit";
1476 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1477 clock-names = "clk_ahb", "clk_xin";
1479 assigned-clocks = <&k3_clks 91 1>;
1480 assigned-clock-parents = <&k3_clks 91 2>;
1481 bus-width = <8>;
1482 mmc-hs200-1_8v;
1483 mmc-ddr-1_8v;
1484 ti,otap-del-sel-legacy = <0x0>;
1485 ti,otap-del-sel-mmc-hs = <0x0>;
1486 ti,otap-del-sel-ddr52 = <0x5>;
1487 ti,otap-del-sel-hs200 = <0x6>;
1488 ti,otap-del-sel-hs400 = <0x0>;
1489 ti,itap-del-sel-legacy = <0x10>;
1490 ti,itap-del-sel-mmc-hs = <0xa>;
1491 ti,itap-del-sel-ddr52 = <0x3>;
1492 ti,trm-icp = <0x8>;
1493 dma-coherent;
1498 compatible = "ti,j721e-sdhci-4bit";
1501 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1502 clock-names = "clk_ahb", "clk_xin";
1504 assigned-clocks = <&k3_clks 92 0>;
1505 assigned-clock-parents = <&k3_clks 92 1>;
1506 ti,otap-del-sel-legacy = <0x0>;
1507 ti,otap-del-sel-sd-hs = <0x0>;
1508 ti,otap-del-sel-sdr12 = <0xf>;
1509 ti,otap-del-sel-sdr25 = <0xf>;
1510 ti,otap-del-sel-sdr50 = <0xc>;
1511 ti,otap-del-sel-ddr50 = <0xc>;
1512 ti,otap-del-sel-sdr104 = <0x5>;
1513 ti,itap-del-sel-legacy = <0x0>;
1514 ti,itap-del-sel-sd-hs = <0x0>;
1515 ti,itap-del-sel-sdr12 = <0x0>;
1516 ti,itap-del-sel-sdr25 = <0x0>;
1517 ti,itap-del-sel-ddr50 = <0x2>;
1518 ti,trm-icp = <0x8>;
1519 ti,clkbuf-sel = <0x7>;
1520 dma-coherent;
1521 sdhci-caps-mask = <0x2 0x0>;
1526 compatible = "ti,j721e-sdhci-4bit";
1529 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1530 clock-names = "clk_ahb", "clk_xin";
1532 assigned-clocks = <&k3_clks 93 0>;
1533 assigned-clock-parents = <&k3_clks 93 1>;
1534 ti,otap-del-sel-legacy = <0x0>;
1535 ti,otap-del-sel-sd-hs = <0x0>;
1536 ti,otap-del-sel-sdr12 = <0xf>;
1537 ti,otap-del-sel-sdr25 = <0xf>;
1538 ti,otap-del-sel-sdr50 = <0xc>;
1539 ti,otap-del-sel-ddr50 = <0xc>;
1540 ti,otap-del-sel-sdr104 = <0x5>;
1541 ti,itap-del-sel-legacy = <0x0>;
1542 ti,itap-del-sel-sd-hs = <0x0>;
1543 ti,itap-del-sel-sdr12 = <0x0>;
1544 ti,itap-del-sel-sdr25 = <0x0>;
1545 ti,itap-del-sel-ddr50 = <0x2>;
1546 ti,trm-icp = <0x8>;
1547 ti,clkbuf-sel = <0x7>;
1548 dma-coherent;
1549 sdhci-caps-mask = <0x2 0x0>;
1553 usbss0: cdns-usb@4104000 {
1554 compatible = "ti,j721e-usb";
1556 dma-coherent;
1557 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1559 clock-names = "ref", "lpm";
1560 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1561 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1562 #address-cells = <2>;
1563 #size-cells = <2>;
1571 reg-names = "otg", "xhci", "dev";
1575 interrupt-names = "host",
1578 maximum-speed = "super-speed";
1583 usbss1: cdns-usb@4114000 {
1584 compatible = "ti,j721e-usb";
1586 dma-coherent;
1587 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1589 clock-names = "ref", "lpm";
1590 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1591 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1592 #address-cells = <2>;
1593 #size-cells = <2>;
1601 reg-names = "otg", "xhci", "dev";
1605 interrupt-names = "host",
1608 maximum-speed = "super-speed";
1614 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1617 #address-cells = <1>;
1618 #size-cells = <0>;
1619 clock-names = "fck";
1621 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1626 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1631 clock-names = "fck";
1633 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1638 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1643 clock-names = "fck";
1645 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1650 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1653 #address-cells = <1>;
1654 #size-cells = <0>;
1655 clock-names = "fck";
1657 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1662 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1665 #address-cells = <1>;
1666 #size-cells = <0>;
1667 clock-names = "fck";
1669 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1674 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1677 #address-cells = <1>;
1678 #size-cells = <0>;
1679 clock-names = "fck";
1681 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1686 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1691 clock-names = "fck";
1693 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1697 ufs_wrapper: ufs-wrapper@4e80000 {
1698 compatible = "ti,j721e-ufs";
1700 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1702 assigned-clocks = <&k3_clks 277 1>;
1703 assigned-clock-parents = <&k3_clks 277 4>;
1705 #address-cells = <2>;
1706 #size-cells = <2>;
1709 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1712 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1714 clock-names = "core_clk", "phy_clk", "ref_clk";
1715 dma-coherent;
1719 mhdp: dp-bridge@a000000 {
1720 compatible = "ti,j721e-mhdp8546";
1727 reg-names = "mhdptx", "j721e-intg";
1731 interrupt-parent = <&gic500>;
1734 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1751 compatible = "ti,j721e-dss";
1774 reg-names = "common_m", "common_s0",
1786 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1788 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1794 interrupt-names = "common_m",
1804 compatible = "ti,am33xx-mcasp-audio";
1807 reg-names = "mpu","dat";
1810 interrupt-names = "tx", "rx";
1813 dma-names = "tx", "rx";
1816 clock-names = "fck";
1817 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1822 compatible = "ti,am33xx-mcasp-audio";
1825 reg-names = "mpu","dat";
1828 interrupt-names = "tx", "rx";
1831 dma-names = "tx", "rx";
1834 clock-names = "fck";
1835 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1840 compatible = "ti,am33xx-mcasp-audio";
1843 reg-names = "mpu","dat";
1846 interrupt-names = "tx", "rx";
1849 dma-names = "tx", "rx";
1852 clock-names = "fck";
1853 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1858 compatible = "ti,am33xx-mcasp-audio";
1861 reg-names = "mpu","dat";
1864 interrupt-names = "tx", "rx";
1867 dma-names = "tx", "rx";
1870 clock-names = "fck";
1871 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1876 compatible = "ti,am33xx-mcasp-audio";
1879 reg-names = "mpu","dat";
1882 interrupt-names = "tx", "rx";
1885 dma-names = "tx", "rx";
1888 clock-names = "fck";
1889 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1894 compatible = "ti,am33xx-mcasp-audio";
1897 reg-names = "mpu","dat";
1900 interrupt-names = "tx", "rx";
1903 dma-names = "tx", "rx";
1906 clock-names = "fck";
1907 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1912 compatible = "ti,am33xx-mcasp-audio";
1915 reg-names = "mpu","dat";
1918 interrupt-names = "tx", "rx";
1921 dma-names = "tx", "rx";
1924 clock-names = "fck";
1925 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1930 compatible = "ti,am33xx-mcasp-audio";
1933 reg-names = "mpu","dat";
1936 interrupt-names = "tx", "rx";
1939 dma-names = "tx", "rx";
1942 clock-names = "fck";
1943 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1948 compatible = "ti,am33xx-mcasp-audio";
1951 reg-names = "mpu","dat";
1954 interrupt-names = "tx", "rx";
1957 dma-names = "tx", "rx";
1960 clock-names = "fck";
1961 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1966 compatible = "ti,am33xx-mcasp-audio";
1969 reg-names = "mpu","dat";
1972 interrupt-names = "tx", "rx";
1975 dma-names = "tx", "rx";
1978 clock-names = "fck";
1979 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1984 compatible = "ti,am33xx-mcasp-audio";
1987 reg-names = "mpu","dat";
1990 interrupt-names = "tx", "rx";
1993 dma-names = "tx", "rx";
1996 clock-names = "fck";
1997 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
2002 compatible = "ti,am33xx-mcasp-audio";
2005 reg-names = "mpu","dat";
2008 interrupt-names = "tx", "rx";
2011 dma-names = "tx", "rx";
2014 clock-names = "fck";
2015 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
2020 compatible = "ti,j7-rti-wdt";
2023 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2024 assigned-clocks = <&k3_clks 252 1>;
2025 assigned-clock-parents = <&k3_clks 252 5>;
2029 compatible = "ti,j7-rti-wdt";
2032 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2033 assigned-clocks = <&k3_clks 253 1>;
2034 assigned-clock-parents = <&k3_clks 253 5>;
2038 compatible = "ti,j721e-r5fss";
2039 ti,cluster-mode = <1>;
2040 #address-cells = <1>;
2041 #size-cells = <1>;
2044 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2047 compatible = "ti,j721e-r5f";
2050 reg-names = "atcm", "btcm";
2051 ti,sci = <&dmsc>;
2052 ti,sci-dev-id = <245>;
2053 ti,sci-proc-ids = <0x06 0xff>;
2055 firmware-name = "j7-main-r5f0_0-fw";
2056 ti,atcm-enable = <1>;
2057 ti,btcm-enable = <1>;
2058 ti,loczrama = <1>;
2062 compatible = "ti,j721e-r5f";
2065 reg-names = "atcm", "btcm";
2066 ti,sci = <&dmsc>;
2067 ti,sci-dev-id = <246>;
2068 ti,sci-proc-ids = <0x07 0xff>;
2070 firmware-name = "j7-main-r5f0_1-fw";
2071 ti,atcm-enable = <1>;
2072 ti,btcm-enable = <1>;
2073 ti,loczrama = <1>;
2078 compatible = "ti,j721e-r5fss";
2079 ti,cluster-mode = <1>;
2080 #address-cells = <1>;
2081 #size-cells = <1>;
2084 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2087 compatible = "ti,j721e-r5f";
2090 reg-names = "atcm", "btcm";
2091 ti,sci = <&dmsc>;
2092 ti,sci-dev-id = <247>;
2093 ti,sci-proc-ids = <0x08 0xff>;
2095 firmware-name = "j7-main-r5f1_0-fw";
2096 ti,atcm-enable = <1>;
2097 ti,btcm-enable = <1>;
2098 ti,loczrama = <1>;
2102 compatible = "ti,j721e-r5f";
2105 reg-names = "atcm", "btcm";
2106 ti,sci = <&dmsc>;
2107 ti,sci-dev-id = <248>;
2108 ti,sci-proc-ids = <0x09 0xff>;
2110 firmware-name = "j7-main-r5f1_1-fw";
2111 ti,atcm-enable = <1>;
2112 ti,btcm-enable = <1>;
2113 ti,loczrama = <1>;
2118 compatible = "ti,j721e-c66-dsp";
2122 reg-names = "l2sram", "l1pram", "l1dram";
2123 ti,sci = <&dmsc>;
2124 ti,sci-dev-id = <142>;
2125 ti,sci-proc-ids = <0x03 0xff>;
2127 firmware-name = "j7-c66_0-fw";
2132 compatible = "ti,j721e-c66-dsp";
2136 reg-names = "l2sram", "l1pram", "l1dram";
2137 ti,sci = <&dmsc>;
2138 ti,sci-dev-id = <143>;
2139 ti,sci-proc-ids = <0x04 0xff>;
2141 firmware-name = "j7-c66_1-fw";
2146 compatible = "ti,j721e-c71-dsp";
2149 reg-names = "l2sram", "l1dram";
2150 ti,sci = <&dmsc>;
2151 ti,sci-dev-id = <15>;
2152 ti,sci-proc-ids = <0x30 0xff>;
2154 firmware-name = "j7-c71_0-fw";
2159 compatible = "ti,j721e-icssg";
2161 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2162 #address-cells = <1>;
2163 #size-cells = <1>;
2170 reg-names = "dram0", "dram1",
2175 compatible = "ti,pruss-cfg", "syscon";
2177 #address-cells = <1>;
2178 #size-cells = <1>;
2182 #address-cells = <1>;
2183 #size-cells = <0>;
2185 icssg0_coreclk_mux: coreclk-mux@3c {
2187 #clock-cells = <0>;
2190 assigned-clocks = <&icssg0_coreclk_mux>;
2191 assigned-clock-parents = <&k3_clks 119 1>;
2194 icssg0_iepclk_mux: iepclk-mux@30 {
2196 #clock-cells = <0>;
2199 assigned-clocks = <&icssg0_iepclk_mux>;
2200 assigned-clock-parents = <&icssg0_coreclk_mux>;
2205 icssg0_mii_rt: mii-rt@32000 {
2206 compatible = "ti,pruss-mii", "syscon";
2210 icssg0_mii_g_rt: mii-g-rt@33000 {
2211 compatible = "ti,pruss-mii-g", "syscon";
2215 icssg0_intc: interrupt-controller@20000 {
2216 compatible = "ti,icssg-intc";
2218 interrupt-controller;
2219 #interrupt-cells = <3>;
2228 interrupt-names = "host_intr0", "host_intr1",
2235 compatible = "ti,j721e-pru";
2239 reg-names = "iram", "control", "debug";
2240 firmware-name = "j7-pru0_0-fw";
2244 compatible = "ti,j721e-rtu";
2248 reg-names = "iram", "control", "debug";
2249 firmware-name = "j7-rtu0_0-fw";
2253 compatible = "ti,j721e-tx-pru";
2257 reg-names = "iram", "control", "debug";
2258 firmware-name = "j7-txpru0_0-fw";
2262 compatible = "ti,j721e-pru";
2266 reg-names = "iram", "control", "debug";
2267 firmware-name = "j7-pru0_1-fw";
2271 compatible = "ti,j721e-rtu";
2275 reg-names = "iram", "control", "debug";
2276 firmware-name = "j7-rtu0_1-fw";
2280 compatible = "ti,j721e-tx-pru";
2284 reg-names = "iram", "control", "debug";
2285 firmware-name = "j7-txpru0_1-fw";
2289 compatible = "ti,davinci_mdio";
2292 clock-names = "fck";
2293 #address-cells = <1>;
2294 #size-cells = <0>;
2301 compatible = "ti,j721e-icssg";
2303 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2304 #address-cells = <1>;
2305 #size-cells = <1>;
2312 reg-names = "dram0", "dram1",
2317 compatible = "ti,pruss-cfg", "syscon";
2319 #address-cells = <1>;
2320 #size-cells = <1>;
2324 #address-cells = <1>;
2325 #size-cells = <0>;
2327 icssg1_coreclk_mux: coreclk-mux@3c {
2329 #clock-cells = <0>;
2332 assigned-clocks = <&icssg1_coreclk_mux>;
2333 assigned-clock-parents = <&k3_clks 120 4>;
2336 icssg1_iepclk_mux: iepclk-mux@30 {
2338 #clock-cells = <0>;
2341 assigned-clocks = <&icssg1_iepclk_mux>;
2342 assigned-clock-parents = <&icssg1_coreclk_mux>;
2347 icssg1_mii_rt: mii-rt@32000 {
2348 compatible = "ti,pruss-mii", "syscon";
2352 icssg1_mii_g_rt: mii-g-rt@33000 {
2353 compatible = "ti,pruss-mii-g", "syscon";
2357 icssg1_intc: interrupt-controller@20000 {
2358 compatible = "ti,icssg-intc";
2360 interrupt-controller;
2361 #interrupt-cells = <3>;
2370 interrupt-names = "host_intr0", "host_intr1",
2377 compatible = "ti,j721e-pru";
2381 reg-names = "iram", "control", "debug";
2382 firmware-name = "j7-pru1_0-fw";
2386 compatible = "ti,j721e-rtu";
2390 reg-names = "iram", "control", "debug";
2391 firmware-name = "j7-rtu1_0-fw";
2395 compatible = "ti,j721e-tx-pru";
2399 reg-names = "iram", "control", "debug";
2400 firmware-name = "j7-txpru1_0-fw";
2404 compatible = "ti,j721e-pru";
2408 reg-names = "iram", "control", "debug";
2409 firmware-name = "j7-pru1_1-fw";
2413 compatible = "ti,j721e-rtu";
2417 reg-names = "iram", "control", "debug";
2418 firmware-name = "j7-rtu1_1-fw";
2422 compatible = "ti,j721e-tx-pru";
2426 reg-names = "iram", "control", "debug";
2427 firmware-name = "j7-txpru1_1-fw";
2431 compatible = "ti,davinci_mdio";
2434 clock-names = "fck";
2435 #address-cells = <1>;
2436 #size-cells = <0>;
2446 reg-names = "m_can", "message_ram";
2447 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2449 clock-names = "hclk", "cclk";
2452 interrupt-names = "int0", "int1";
2453 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2461 reg-names = "m_can", "message_ram";
2462 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2464 clock-names = "hclk", "cclk";
2467 interrupt-names = "int0", "int1";
2468 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2476 reg-names = "m_can", "message_ram";
2477 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2479 clock-names = "hclk", "cclk";
2482 interrupt-names = "int0", "int1";
2483 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2491 reg-names = "m_can", "message_ram";
2492 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2494 clock-names = "hclk", "cclk";
2497 interrupt-names = "int0", "int1";
2498 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2506 reg-names = "m_can", "message_ram";
2507 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2509 clock-names = "hclk", "cclk";
2512 interrupt-names = "int0", "int1";
2513 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2521 reg-names = "m_can", "message_ram";
2522 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2524 clock-names = "hclk", "cclk";
2527 interrupt-names = "int0", "int1";
2528 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2536 reg-names = "m_can", "message_ram";
2537 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2539 clock-names = "hclk", "cclk";
2542 interrupt-names = "int0", "int1";
2543 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2551 reg-names = "m_can", "message_ram";
2552 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2554 clock-names = "hclk", "cclk";
2557 interrupt-names = "int0", "int1";
2558 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2566 reg-names = "m_can", "message_ram";
2567 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2569 clock-names = "hclk", "cclk";
2572 interrupt-names = "int0", "int1";
2573 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2581 reg-names = "m_can", "message_ram";
2582 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2584 clock-names = "hclk", "cclk";
2587 interrupt-names = "int0", "int1";
2588 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2596 reg-names = "m_can", "message_ram";
2597 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2599 clock-names = "hclk", "cclk";
2602 interrupt-names = "int0", "int1";
2603 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2611 reg-names = "m_can", "message_ram";
2612 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2614 clock-names = "hclk", "cclk";
2617 interrupt-names = "int0", "int1";
2618 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2626 reg-names = "m_can", "message_ram";
2627 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2629 clock-names = "hclk", "cclk";
2632 interrupt-names = "int0", "int1";
2633 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2641 reg-names = "m_can", "message_ram";
2642 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2644 clock-names = "hclk", "cclk";
2647 interrupt-names = "int0", "int1";
2648 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2653 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2656 #address-cells = <1>;
2657 #size-cells = <0>;
2658 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2664 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2667 #address-cells = <1>;
2668 #size-cells = <0>;
2669 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2675 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2678 #address-cells = <1>;
2679 #size-cells = <0>;
2680 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2686 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2689 #address-cells = <1>;
2690 #size-cells = <0>;
2691 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2697 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2700 #address-cells = <1>;
2701 #size-cells = <0>;
2702 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2708 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2711 #address-cells = <1>;
2712 #size-cells = <0>;
2713 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2719 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2722 #address-cells = <1>;
2723 #size-cells = <0>;
2724 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2730 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2733 #address-cells = <1>;
2734 #size-cells = <0>;
2735 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2741 compatible = "ti,j721e-esm";
2743 ti,esm-pins = <344>, <345>;