Lines Matching +full:0 +full:xc400
15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
49 reg = <0x00004080 0x50>;
51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
52 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
54 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
55 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
68 reg = <0x4044 0x20>;
75 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
76 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
81 reg = <0x4140 0x18>;
89 reg = <0x00 0x3000000 0x00 0x100>;
91 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
99 reg = <0x00 0x3010000 0x00 0x100>;
101 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
109 reg = <0x00 0x3020000 0x00 0x100>;
111 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
119 reg = <0x00 0x3030000 0x00 0x100>;
121 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
129 reg = <0x00 0x3040000 0x00 0x100>;
131 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
139 reg = <0x00 0x3050000 0x00 0x100>;
141 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
153 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
154 <0x00 0x01900000 0x00 0x100000>, /* GICR */
155 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
156 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
157 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
164 reg = <0x00 0x01820000 0x00 0x10000>;
165 socionext,synquacer-pre-its = <0x1000000 0x400000>;
173 reg = <0x00 0x00a00000 0x00 0x800>;
187 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
195 reg = <0x0 0x310e0000 0x0 0x4000>;
202 ti,interrupt-ranges = <0 64 64>,
209 reg = <0x0 0x33d00000 0x0 0x100000>;
213 #interrupt-cells = <0>;
216 ti,interrupt-ranges = <0 0 256>;
223 reg = <0x00 0x32c00000 0x00 0x100000>,
224 <0x00 0x32400000 0x00 0x100000>,
225 <0x00 0x32800000 0x00 0x100000>;
232 reg = <0x0 0x36600000 0x0 0x100000>;
242 reg = <0x00 0x30e00000 0x00 0x1000>;
248 reg = <0x00 0x31f80000 0x00 0x200>;
258 reg = <0x00 0x31f81000 0x00 0x200>;
268 reg = <0x00 0x31f82000 0x00 0x200>;
278 reg = <0x00 0x31f83000 0x00 0x200>;
288 reg = <0x00 0x31f84000 0x00 0x200>;
298 reg = <0x00 0x31f85000 0x00 0x200>;
308 reg = <0x00 0x31f86000 0x00 0x200>;
318 reg = <0x00 0x31f87000 0x00 0x200>;
328 reg = <0x00 0x31f88000 0x00 0x200>;
338 reg = <0x00 0x31f89000 0x00 0x200>;
348 reg = <0x00 0x31f8a000 0x00 0x200>;
358 reg = <0x00 0x31f8b000 0x00 0x200>;
368 reg = <0x0 0x3c000000 0x0 0x400000>,
369 <0x0 0x38000000 0x0 0x400000>,
370 <0x0 0x31120000 0x0 0x100>,
371 <0x0 0x33000000 0x0 0x40000>,
372 <0x0 0x31080000 0x0 0x40000>;
375 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
383 reg = <0x0 0x31150000 0x0 0x100>,
384 <0x0 0x34000000 0x0 0x100000>,
385 <0x0 0x35000000 0x0 0x100000>,
386 <0x0 0x30b00000 0x0 0x20000>,
387 <0x0 0x30c00000 0x0 0x10000>,
388 <0x0 0x30d00000 0x0 0x8000>;
398 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
399 <0x0f>, /* TX_HCHAN */
400 <0x10>; /* TX_UHCHAN */
401 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
402 <0x0b>, /* RX_HCHAN */
403 <0x0c>; /* RX_UHCHAN */
404 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
409 reg = <0x0 0x310d0000 0x0 0x400>;
424 reg = <0x0 0xc000000 0x0 0x200000>;
426 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
431 dmas = <&main_udmap 0xca00>,
432 <&main_udmap 0xca01>,
433 <&main_udmap 0xca02>,
434 <&main_udmap 0xca03>,
435 <&main_udmap 0xca04>,
436 <&main_udmap 0xca05>,
437 <&main_udmap 0xca06>,
438 <&main_udmap 0xca07>,
439 <&main_udmap 0x4a00>;
448 #size-cells = <0>;
508 reg = <0x0 0xf00 0x0 0x100>;
510 #size-cells = <0>;
519 reg = <0x0 0x3d000 0x0 0x400>;
531 reg = <0x0 0x4e00000 0x0 0x1200>;
535 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
537 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
538 <&main_udmap 0x4001>;
543 reg = <0x0 0x4e10000 0x0 0x7d>;
550 /* Proxy 0 addressing */
551 reg = <0x0 0x11c000 0x0 0x2b4>;
554 pinctrl-single,function-mask = <0xffffffff>;
560 reg = <0x00 0x104200 0x00 0x50>;
563 pinctrl-single,function-mask = <0x00000007>;
569 reg = <0x00 0x104280 0x00 0x20>;
572 pinctrl-single,function-mask = <0x0000001f>;
582 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
586 ranges = <0x5000000 0x0 0x5000000 0x10000>;
590 #clock-cells = <0>;
596 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
597 #clock-cells = <0>;
599 assigned-clock-parents = <&k3_clks 292 0>;
603 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
604 #clock-cells = <0>;
611 #clock-cells = <0>;
616 #clock-cells = <0>;
622 reg = <0x5000000 0x10000>;
624 #size-cells = <0>;
626 resets = <&serdes_wiz0 0>;
642 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
646 ranges = <0x5010000 0x0 0x5010000 0x10000>;
650 #clock-cells = <0>;
656 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
657 #clock-cells = <0>;
659 assigned-clock-parents = <&k3_clks 293 0>;
663 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
664 #clock-cells = <0>;
671 #clock-cells = <0>;
676 #clock-cells = <0>;
682 reg = <0x5010000 0x10000>;
684 #size-cells = <0>;
686 resets = <&serdes_wiz1 0>;
702 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
706 ranges = <0x5020000 0x0 0x5020000 0x10000>;
710 #clock-cells = <0>;
716 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
717 #clock-cells = <0>;
719 assigned-clock-parents = <&k3_clks 294 0>;
723 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
724 #clock-cells = <0>;
731 #clock-cells = <0>;
736 #clock-cells = <0>;
742 reg = <0x5020000 0x10000>;
744 #size-cells = <0>;
746 resets = <&serdes_wiz2 0>;
762 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
766 ranges = <0x5030000 0x0 0x5030000 0x10000>;
770 #clock-cells = <0>;
776 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
777 #clock-cells = <0>;
779 assigned-clock-parents = <&k3_clks 295 0>;
783 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
784 #clock-cells = <0>;
791 #clock-cells = <0>;
796 #clock-cells = <0>;
802 reg = <0x5030000 0x10000>;
804 #size-cells = <0>;
806 resets = <&serdes_wiz3 0>;
817 reg = <0x00 0x02900000 0x00 0x1000>,
818 <0x00 0x02907000 0x00 0x400>,
819 <0x00 0x0d000000 0x00 0x00800000>,
820 <0x00 0x10000000 0x00 0x00001000>;
825 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
833 bus-range = <0x0 0xff>;
834 vendor-id = <0x104c>;
835 device-id = <0xb00d>;
836 msi-map = <0x0 &gic_its 0x0 0x10000>;
838 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
839 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
840 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
846 reg = <0x00 0x02910000 0x00 0x1000>,
847 <0x00 0x02917000 0x00 0x400>,
848 <0x00 0x0d800000 0x00 0x00800000>,
849 <0x00 0x18000000 0x00 0x00001000>;
854 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
862 bus-range = <0x0 0xff>;
863 vendor-id = <0x104c>;
864 device-id = <0xb00d>;
865 msi-map = <0x0 &gic_its 0x10000 0x10000>;
867 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
868 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
869 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
875 reg = <0x00 0x02920000 0x00 0x1000>,
876 <0x00 0x02927000 0x00 0x400>,
877 <0x00 0x0e000000 0x00 0x00800000>,
878 <0x44 0x00000000 0x00 0x00001000>;
883 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
891 bus-range = <0x0 0xff>;
892 vendor-id = <0x104c>;
893 device-id = <0xb00d>;
894 msi-map = <0x0 &gic_its 0x20000 0x10000>;
896 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
897 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
898 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
904 reg = <0x00 0x02930000 0x00 0x1000>,
905 <0x00 0x02937000 0x00 0x400>,
906 <0x00 0x0e800000 0x00 0x00800000>,
907 <0x44 0x10000000 0x00 0x00001000>;
912 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
920 bus-range = <0x0 0xff>;
921 vendor-id = <0x104c>;
922 device-id = <0xb00d>;
923 msi-map = <0x0 &gic_its 0x30000 0x10000>;
925 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
926 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
927 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
944 ranges = <0x05050000 0x00 0x05050000 0x010000>,
945 <0x0a030a00 0x00 0x0a030a00 0x40>;
953 reg = <0x05050000 0x010000>,
954 <0x0a030a00 0x40>; /* DPTX PHY */
957 resets = <&serdes_wiz4 0>;
968 #size-cells = <0>;
974 reg = <0x00 0x2400000 0x00 0x400>;
986 reg = <0x00 0x2410000 0x00 0x400>;
990 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
998 reg = <0x00 0x2420000 0x00 0x400>;
1010 reg = <0x00 0x2430000 0x00 0x400>;
1014 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1022 reg = <0x00 0x2440000 0x00 0x400>;
1034 reg = <0x00 0x2450000 0x00 0x400>;
1038 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1046 reg = <0x00 0x2460000 0x00 0x400>;
1058 reg = <0x00 0x2470000 0x00 0x400>;
1062 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1070 reg = <0x00 0x2480000 0x00 0x400>;
1082 reg = <0x00 0x2490000 0x00 0x400>;
1086 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1094 reg = <0x00 0x24a0000 0x00 0x400>;
1106 reg = <0x00 0x24b0000 0x00 0x400>;
1110 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1118 reg = <0x00 0x24c0000 0x00 0x400>;
1130 reg = <0x00 0x24d0000 0x00 0x400>;
1134 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1142 reg = <0x00 0x24e0000 0x00 0x400>;
1154 reg = <0x00 0x24f0000 0x00 0x400>;
1158 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1166 reg = <0x00 0x2500000 0x00 0x400>;
1178 reg = <0x00 0x2510000 0x00 0x400>;
1182 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1190 reg = <0x00 0x2520000 0x00 0x400>;
1202 reg = <0x00 0x2530000 0x00 0x400>;
1206 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1214 reg = <0x00 0x02800000 0x00 0x100>;
1219 clocks = <&k3_clks 146 0>;
1226 reg = <0x00 0x02810000 0x00 0x100>;
1231 clocks = <&k3_clks 278 0>;
1238 reg = <0x00 0x02820000 0x00 0x100>;
1243 clocks = <&k3_clks 279 0>;
1250 reg = <0x00 0x02830000 0x00 0x100>;
1255 clocks = <&k3_clks 280 0>;
1262 reg = <0x00 0x02840000 0x00 0x100>;
1267 clocks = <&k3_clks 281 0>;
1274 reg = <0x00 0x02850000 0x00 0x100>;
1279 clocks = <&k3_clks 282 0>;
1286 reg = <0x00 0x02860000 0x00 0x100>;
1291 clocks = <&k3_clks 283 0>;
1298 reg = <0x00 0x02870000 0x00 0x100>;
1303 clocks = <&k3_clks 284 0>;
1310 reg = <0x00 0x02880000 0x00 0x100>;
1315 clocks = <&k3_clks 285 0>;
1322 reg = <0x00 0x02890000 0x00 0x100>;
1327 clocks = <&k3_clks 286 0>;
1334 reg = <0x0 0x00600000 0x0 0x100>;
1343 ti,davinci-gpio-unbanked = <0>;
1345 clocks = <&k3_clks 105 0>;
1352 reg = <0x0 0x00601000 0x0 0x100>;
1360 ti,davinci-gpio-unbanked = <0>;
1362 clocks = <&k3_clks 106 0>;
1369 reg = <0x0 0x00610000 0x0 0x100>;
1378 ti,davinci-gpio-unbanked = <0>;
1380 clocks = <&k3_clks 107 0>;
1387 reg = <0x0 0x00611000 0x0 0x100>;
1395 ti,davinci-gpio-unbanked = <0>;
1397 clocks = <&k3_clks 108 0>;
1404 reg = <0x0 0x00620000 0x0 0x100>;
1413 ti,davinci-gpio-unbanked = <0>;
1415 clocks = <&k3_clks 109 0>;
1422 reg = <0x0 0x00621000 0x0 0x100>;
1430 ti,davinci-gpio-unbanked = <0>;
1432 clocks = <&k3_clks 110 0>;
1439 reg = <0x0 0x00630000 0x0 0x100>;
1448 ti,davinci-gpio-unbanked = <0>;
1450 clocks = <&k3_clks 111 0>;
1457 reg = <0x0 0x00631000 0x0 0x100>;
1465 ti,davinci-gpio-unbanked = <0>;
1467 clocks = <&k3_clks 112 0>;
1474 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1478 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1484 ti,otap-del-sel-legacy = <0x0>;
1485 ti,otap-del-sel-mmc-hs = <0x0>;
1486 ti,otap-del-sel-ddr52 = <0x5>;
1487 ti,otap-del-sel-hs200 = <0x6>;
1488 ti,otap-del-sel-hs400 = <0x0>;
1489 ti,itap-del-sel-legacy = <0x10>;
1490 ti,itap-del-sel-mmc-hs = <0xa>;
1491 ti,itap-del-sel-ddr52 = <0x3>;
1492 ti,trm-icp = <0x8>;
1499 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1503 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1504 assigned-clocks = <&k3_clks 92 0>;
1506 ti,otap-del-sel-legacy = <0x0>;
1507 ti,otap-del-sel-sd-hs = <0x0>;
1508 ti,otap-del-sel-sdr12 = <0xf>;
1509 ti,otap-del-sel-sdr25 = <0xf>;
1510 ti,otap-del-sel-sdr50 = <0xc>;
1511 ti,otap-del-sel-ddr50 = <0xc>;
1512 ti,otap-del-sel-sdr104 = <0x5>;
1513 ti,itap-del-sel-legacy = <0x0>;
1514 ti,itap-del-sel-sd-hs = <0x0>;
1515 ti,itap-del-sel-sdr12 = <0x0>;
1516 ti,itap-del-sel-sdr25 = <0x0>;
1517 ti,itap-del-sel-ddr50 = <0x2>;
1518 ti,trm-icp = <0x8>;
1519 ti,clkbuf-sel = <0x7>;
1521 sdhci-caps-mask = <0x2 0x0>;
1527 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1531 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1532 assigned-clocks = <&k3_clks 93 0>;
1534 ti,otap-del-sel-legacy = <0x0>;
1535 ti,otap-del-sel-sd-hs = <0x0>;
1536 ti,otap-del-sel-sdr12 = <0xf>;
1537 ti,otap-del-sel-sdr25 = <0xf>;
1538 ti,otap-del-sel-sdr50 = <0xc>;
1539 ti,otap-del-sel-ddr50 = <0xc>;
1540 ti,otap-del-sel-sdr104 = <0x5>;
1541 ti,itap-del-sel-legacy = <0x0>;
1542 ti,itap-del-sel-sd-hs = <0x0>;
1543 ti,itap-del-sel-sdr12 = <0x0>;
1544 ti,itap-del-sel-sdr25 = <0x0>;
1545 ti,itap-del-sel-ddr50 = <0x2>;
1546 ti,trm-icp = <0x8>;
1547 ti,clkbuf-sel = <0x7>;
1549 sdhci-caps-mask = <0x2 0x0>;
1555 reg = <0x00 0x4104000 0x00 0x100>;
1568 reg = <0x00 0x6000000 0x00 0x10000>,
1569 <0x00 0x6010000 0x00 0x10000>,
1570 <0x00 0x6020000 0x00 0x10000>;
1572 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1574 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1585 reg = <0x00 0x4114000 0x00 0x100>;
1598 reg = <0x00 0x6400000 0x00 0x10000>,
1599 <0x00 0x6410000 0x00 0x10000>,
1600 <0x00 0x6420000 0x00 0x10000>;
1602 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1604 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1615 reg = <0x0 0x2000000 0x0 0x100>;
1618 #size-cells = <0>;
1620 clocks = <&k3_clks 187 0>;
1627 reg = <0x0 0x2010000 0x0 0x100>;
1630 #size-cells = <0>;
1632 clocks = <&k3_clks 188 0>;
1639 reg = <0x0 0x2020000 0x0 0x100>;
1642 #size-cells = <0>;
1644 clocks = <&k3_clks 189 0>;
1651 reg = <0x0 0x2030000 0x0 0x100>;
1654 #size-cells = <0>;
1656 clocks = <&k3_clks 190 0>;
1663 reg = <0x0 0x2040000 0x0 0x100>;
1666 #size-cells = <0>;
1668 clocks = <&k3_clks 191 0>;
1675 reg = <0x0 0x2050000 0x0 0x100>;
1678 #size-cells = <0>;
1680 clocks = <&k3_clks 192 0>;
1687 reg = <0x0 0x2060000 0x0 0x100>;
1690 #size-cells = <0>;
1692 clocks = <&k3_clks 193 0>;
1699 reg = <0x0 0x4e80000 0x0 0x100>;
1710 reg = <0x0 0x4e84000 0x0 0x10000>;
1713 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1725 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1726 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1738 #size-cells = <0>;
1740 port@0 {
1741 reg = <0>;
1753 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1754 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1755 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1756 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1758 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1759 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1760 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1761 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1763 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1764 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1765 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1766 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1768 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1769 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1770 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1771 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1772 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1781 clocks = <&k3_clks 152 0>,
1805 reg = <0x0 0x02b00000 0x0 0x2000>,
1806 <0x0 0x02b08000 0x0 0x1000>;
1812 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1823 reg = <0x0 0x02b10000 0x0 0x2000>,
1824 <0x0 0x02b18000 0x0 0x1000>;
1830 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1841 reg = <0x0 0x02b20000 0x0 0x2000>,
1842 <0x0 0x02b28000 0x0 0x1000>;
1848 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1859 reg = <0x0 0x02b30000 0x0 0x2000>,
1860 <0x0 0x02b38000 0x0 0x1000>;
1866 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1877 reg = <0x0 0x02b40000 0x0 0x2000>,
1878 <0x0 0x02b48000 0x0 0x1000>;
1884 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1895 reg = <0x0 0x02b50000 0x0 0x2000>,
1896 <0x0 0x02b58000 0x0 0x1000>;
1902 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1913 reg = <0x0 0x02b60000 0x0 0x2000>,
1914 <0x0 0x02b68000 0x0 0x1000>;
1920 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1931 reg = <0x0 0x02b70000 0x0 0x2000>,
1932 <0x0 0x02b78000 0x0 0x1000>;
1938 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1949 reg = <0x0 0x02b80000 0x0 0x2000>,
1950 <0x0 0x02b88000 0x0 0x1000>;
1956 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1967 reg = <0x0 0x02b90000 0x0 0x2000>,
1968 <0x0 0x02b98000 0x0 0x1000>;
1974 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1985 reg = <0x0 0x02ba0000 0x0 0x2000>,
1986 <0x0 0x02ba8000 0x0 0x1000>;
1992 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
2003 reg = <0x0 0x02bb0000 0x0 0x2000>,
2004 <0x0 0x02bb8000 0x0 0x1000>;
2010 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2021 reg = <0x0 0x2200000 0x0 0x100>;
2030 reg = <0x0 0x2210000 0x0 0x100>;
2042 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2043 <0x5d00000 0x00 0x5d00000 0x20000>;
2048 reg = <0x5c00000 0x00008000>,
2049 <0x5c10000 0x00008000>;
2053 ti,sci-proc-ids = <0x06 0xff>;
2063 reg = <0x5d00000 0x00008000>,
2064 <0x5d10000 0x00008000>;
2068 ti,sci-proc-ids = <0x07 0xff>;
2082 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2083 <0x5f00000 0x00 0x5f00000 0x20000>;
2088 reg = <0x5e00000 0x00008000>,
2089 <0x5e10000 0x00008000>;
2093 ti,sci-proc-ids = <0x08 0xff>;
2103 reg = <0x5f00000 0x00008000>,
2104 <0x5f10000 0x00008000>;
2108 ti,sci-proc-ids = <0x09 0xff>;
2119 reg = <0x4d 0x80800000 0x00 0x00048000>,
2120 <0x4d 0x80e00000 0x00 0x00008000>,
2121 <0x4d 0x80f00000 0x00 0x00008000>;
2125 ti,sci-proc-ids = <0x03 0xff>;
2133 reg = <0x4d 0x81800000 0x00 0x00048000>,
2134 <0x4d 0x81e00000 0x00 0x00008000>,
2135 <0x4d 0x81f00000 0x00 0x00008000>;
2139 ti,sci-proc-ids = <0x04 0xff>;
2147 reg = <0x00 0x64800000 0x00 0x00080000>,
2148 <0x00 0x64e00000 0x00 0x0000c000>;
2152 ti,sci-proc-ids = <0x30 0xff>;
2160 reg = <0x00 0xb000000 0x00 0x80000>;
2164 ranges = <0x0 0x00 0x0b000000 0x100000>;
2166 icssg0_mem: memories@0 {
2167 reg = <0x0 0x2000>,
2168 <0x2000 0x2000>,
2169 <0x10000 0x10000>;
2176 reg = <0x26000 0x200>;
2179 ranges = <0x0 0x26000 0x2000>;
2183 #size-cells = <0>;
2186 reg = <0x3c>;
2187 #clock-cells = <0>;
2195 reg = <0x30>;
2196 #clock-cells = <0>;
2207 reg = <0x32000 0x100>;
2212 reg = <0x33000 0x1000>;
2217 reg = <0x20000 0x2000>;
2236 reg = <0x34000 0x3000>,
2237 <0x22000 0x100>,
2238 <0x22400 0x100>;
2245 reg = <0x4000 0x2000>,
2246 <0x23000 0x100>,
2247 <0x23400 0x100>;
2254 reg = <0xa000 0x1800>,
2255 <0x25000 0x100>,
2256 <0x25400 0x100>;
2263 reg = <0x38000 0x3000>,
2264 <0x24000 0x100>,
2265 <0x24400 0x100>;
2272 reg = <0x6000 0x2000>,
2273 <0x23800 0x100>,
2274 <0x23c00 0x100>;
2281 reg = <0xc000 0x1800>,
2282 <0x25800 0x100>,
2283 <0x25c00 0x100>;
2290 reg = <0x32400 0x100>;
2294 #size-cells = <0>;
2302 reg = <0x00 0xb100000 0x00 0x80000>;
2306 ranges = <0x0 0x00 0x0b100000 0x100000>;
2309 reg = <0x0 0x2000>,
2310 <0x2000 0x2000>,
2311 <0x10000 0x10000>;
2318 reg = <0x26000 0x200>;
2321 ranges = <0x0 0x26000 0x2000>;
2325 #size-cells = <0>;
2328 reg = <0x3c>;
2329 #clock-cells = <0>;
2337 reg = <0x30>;
2338 #clock-cells = <0>;
2349 reg = <0x32000 0x100>;
2354 reg = <0x33000 0x1000>;
2359 reg = <0x20000 0x2000>;
2378 reg = <0x34000 0x4000>,
2379 <0x22000 0x100>,
2380 <0x22400 0x100>;
2387 reg = <0x4000 0x2000>,
2388 <0x23000 0x100>,
2389 <0x23400 0x100>;
2396 reg = <0xa000 0x1800>,
2397 <0x25000 0x100>,
2398 <0x25400 0x100>;
2405 reg = <0x38000 0x4000>,
2406 <0x24000 0x100>,
2407 <0x24400 0x100>;
2414 reg = <0x6000 0x2000>,
2415 <0x23800 0x100>,
2416 <0x23c00 0x100>;
2423 reg = <0xc000 0x1800>,
2424 <0x25800 0x100>,
2425 <0x25c00 0x100>;
2432 reg = <0x32400 0x100>;
2436 #size-cells = <0>;
2444 reg = <0x00 0x02701000 0x00 0x200>,
2445 <0x00 0x02708000 0x00 0x8000>;
2448 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2453 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2459 reg = <0x00 0x02711000 0x00 0x200>,
2460 <0x00 0x02718000 0x00 0x8000>;
2463 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2468 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2474 reg = <0x00 0x02721000 0x00 0x200>,
2475 <0x00 0x02728000 0x00 0x8000>;
2478 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2483 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2489 reg = <0x00 0x02731000 0x00 0x200>,
2490 <0x00 0x02738000 0x00 0x8000>;
2493 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2498 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2504 reg = <0x00 0x02741000 0x00 0x200>,
2505 <0x00 0x02748000 0x00 0x8000>;
2508 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2513 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2519 reg = <0x00 0x02751000 0x00 0x200>,
2520 <0x00 0x02758000 0x00 0x8000>;
2523 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2528 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2534 reg = <0x00 0x02761000 0x00 0x200>,
2535 <0x00 0x02768000 0x00 0x8000>;
2538 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2543 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2549 reg = <0x00 0x02771000 0x00 0x200>,
2550 <0x00 0x02778000 0x00 0x8000>;
2553 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2558 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2564 reg = <0x00 0x02781000 0x00 0x200>,
2565 <0x00 0x02788000 0x00 0x8000>;
2568 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2573 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2579 reg = <0x00 0x02791000 0x00 0x200>,
2580 <0x00 0x02798000 0x00 0x8000>;
2583 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2588 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2594 reg = <0x00 0x027a1000 0x00 0x200>,
2595 <0x00 0x027a8000 0x00 0x8000>;
2598 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2603 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2609 reg = <0x00 0x027b1000 0x00 0x200>,
2610 <0x00 0x027b8000 0x00 0x8000>;
2613 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2618 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2624 reg = <0x00 0x027c1000 0x00 0x200>,
2625 <0x00 0x027c8000 0x00 0x8000>;
2628 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2633 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2639 reg = <0x00 0x027d1000 0x00 0x200>,
2640 <0x00 0x027d8000 0x00 0x8000>;
2643 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2648 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2654 reg = <0x00 0x02100000 0x00 0x400>;
2657 #size-cells = <0>;
2665 reg = <0x00 0x02110000 0x00 0x400>;
2668 #size-cells = <0>;
2676 reg = <0x00 0x02120000 0x00 0x400>;
2679 #size-cells = <0>;
2687 reg = <0x00 0x02130000 0x00 0x400>;
2690 #size-cells = <0>;
2698 reg = <0x00 0x02140000 0x00 0x400>;
2701 #size-cells = <0>;
2709 reg = <0x00 0x02150000 0x00 0x400>;
2712 #size-cells = <0>;
2720 reg = <0x00 0x02160000 0x00 0x400>;
2723 #size-cells = <0>;
2731 reg = <0x00 0x02170000 0x00 0x400>;
2734 #size-cells = <0>;
2742 reg = <0x0 0x700000 0x0 0x1000>;