Lines Matching +full:synquacer +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "mmio-mux";
37 #mux-control-cells = <1>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
44 ti,qsgmii-main-ports = <1>;
46 #phy-cells = <1>;
49 usb_serdes_mux: mux-controller@4000 {
50 compatible = "mmio-mux";
51 #mux-control-cells = <1>;
52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
56 gic500: interrupt-controller@1800000 {
57 compatible = "arm,gic-v3";
58 #address-cells = <2>;
59 #size-cells = <2>;
61 #interrupt-cells = <3>;
62 interrupt-controller;
72 gic_its: msi-controller@1820000 {
73 compatible = "arm,gic-v3-its";
75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
76 msi-controller;
77 #msi-cells = <1>;
81 main_gpio_intr: interrupt-controller@a00000 {
82 compatible = "ti,sci-intr";
84 ti,intr-trigger-type = <1>;
85 interrupt-controller;
86 interrupt-parent = <&gic500>;
87 #interrupt-cells = <1>;
89 ti,sci-dev-id = <131>;
90 ti,interrupt-ranges = <8 392 56>;
94 compatible = "simple-bus";
95 #address-cells = <2>;
96 #size-cells = <2>;
98 ti,sci-dev-id = <199>;
99 dma-coherent;
100 dma-ranges;
102 main_navss_intr: interrupt-controller@310e0000 {
103 compatible = "ti,sci-intr";
105 ti,intr-trigger-type = <4>;
106 interrupt-controller;
107 interrupt-parent = <&gic500>;
108 #interrupt-cells = <1>;
110 ti,sci-dev-id = <213>;
111 ti,interrupt-ranges = <0 64 64>,
116 main_udmass_inta: msi-controller@33d00000 {
117 compatible = "ti,sci-inta";
119 interrupt-controller;
120 #interrupt-cells = <0>;
121 interrupt-parent = <&main_navss_intr>;
122 msi-controller;
124 ti,sci-dev-id = <209>;
125 ti,interrupt-ranges = <0 0 256>;
129 compatible = "ti,am654-secure-proxy";
130 #mbox-cells = <1>;
131 reg-names = "target_data", "rt", "scfg";
135 interrupt-names = "rx_011";
140 compatible = "ti,am654-hwspinlock";
142 #hwlock-cells = <1>;
146 compatible = "ti,am654-mailbox";
148 #mbox-cells = <1>;
149 ti,mbox-num-users = <4>;
150 ti,mbox-num-fifos = <16>;
151 interrupt-parent = <&main_navss_intr>;
156 compatible = "ti,am654-mailbox";
158 #mbox-cells = <1>;
159 ti,mbox-num-users = <4>;
160 ti,mbox-num-fifos = <16>;
161 interrupt-parent = <&main_navss_intr>;
166 compatible = "ti,am654-mailbox";
168 #mbox-cells = <1>;
169 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <16>;
171 interrupt-parent = <&main_navss_intr>;
176 compatible = "ti,am654-mailbox";
178 #mbox-cells = <1>;
179 ti,mbox-num-users = <4>;
180 ti,mbox-num-fifos = <16>;
181 interrupt-parent = <&main_navss_intr>;
186 compatible = "ti,am654-mailbox";
188 #mbox-cells = <1>;
189 ti,mbox-num-users = <4>;
190 ti,mbox-num-fifos = <16>;
191 interrupt-parent = <&main_navss_intr>;
196 compatible = "ti,am654-mailbox";
198 #mbox-cells = <1>;
199 ti,mbox-num-users = <4>;
200 ti,mbox-num-fifos = <16>;
201 interrupt-parent = <&main_navss_intr>;
206 compatible = "ti,am654-mailbox";
208 #mbox-cells = <1>;
209 ti,mbox-num-users = <4>;
210 ti,mbox-num-fifos = <16>;
211 interrupt-parent = <&main_navss_intr>;
216 compatible = "ti,am654-mailbox";
218 #mbox-cells = <1>;
219 ti,mbox-num-users = <4>;
220 ti,mbox-num-fifos = <16>;
221 interrupt-parent = <&main_navss_intr>;
226 compatible = "ti,am654-mailbox";
228 #mbox-cells = <1>;
229 ti,mbox-num-users = <4>;
230 ti,mbox-num-fifos = <16>;
231 interrupt-parent = <&main_navss_intr>;
236 compatible = "ti,am654-mailbox";
238 #mbox-cells = <1>;
239 ti,mbox-num-users = <4>;
240 ti,mbox-num-fifos = <16>;
241 interrupt-parent = <&main_navss_intr>;
246 compatible = "ti,am654-mailbox";
248 #mbox-cells = <1>;
249 ti,mbox-num-users = <4>;
250 ti,mbox-num-fifos = <16>;
251 interrupt-parent = <&main_navss_intr>;
256 compatible = "ti,am654-mailbox";
258 #mbox-cells = <1>;
259 ti,mbox-num-users = <4>;
260 ti,mbox-num-fifos = <16>;
261 interrupt-parent = <&main_navss_intr>;
266 compatible = "ti,am654-navss-ringacc";
272 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
273 ti,num-rings = <1024>;
274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
276 ti,sci-dev-id = <211>;
277 msi-parent = <&main_udmass_inta>;
280 main_udmap: dma-controller@31150000 {
281 compatible = "ti,j721e-navss-main-udmap";
288 reg-names = "gcfg", "rchanrt", "tchanrt",
290 msi-parent = <&main_udmass_inta>;
291 #dma-cells = <1>;
294 ti,sci-dev-id = <212>;
297 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
300 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
303 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
307 compatible = "ti,j721e-cpts";
309 reg-names = "cpts";
311 clock-names = "cpts";
312 interrupts-extended = <&main_navss_intr 391>;
313 interrupt-names = "cpts";
314 ti,cpts-periodic-outputs = <6>;
315 ti,cpts-ext-ts-inputs = <8>;
320 compatible = "ti,j7200-cpswxg-nuss";
321 #address-cells = <2>;
322 #size-cells = <2>;
324 reg-names = "cpsw_nuss";
327 clock-names = "fck";
328 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
339 dma-names = "tx0", "tx1", "tx2", "tx3",
345 ethernet-ports {
346 #address-cells = <1>;
347 #size-cells = <0>;
350 ti,mac-only;
357 ti,mac-only;
364 ti,mac-only;
371 ti,mac-only;
378 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
380 #address-cells = <1>;
381 #size-cells = <0>;
383 clock-names = "fck";
389 compatible = "ti,j721e-cpts";
392 clock-names = "cpts";
393 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-names = "cpts";
395 ti,cpts-ext-ts-inputs = <4>;
396 ti,cpts-periodic-outputs = <2>;
402 compatible = "pinctrl-single";
404 #pinctrl-cells = <1>;
405 pinctrl-single,register-width = <32>;
406 pinctrl-single,function-mask = <0x000001ff>;
411 compatible = "pinctrl-single";
413 #pinctrl-cells = <1>;
414 pinctrl-single,register-width = <32>;
415 pinctrl-single,function-mask = <0x0000001f>;
419 compatible = "pinctrl-single";
422 #pinctrl-cells = <1>;
423 pinctrl-single,register-width = <32>;
424 pinctrl-single,function-mask = <0xffffffff>;
428 compatible = "pinctrl-single";
431 #pinctrl-cells = <1>;
432 pinctrl-single,register-width = <32>;
433 pinctrl-single,function-mask = <0xffffffff>;
437 compatible = "ti,j721e-uart", "ti,am654-uart";
440 clock-frequency = <48000000>;
441 current-speed = <115200>;
442 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
444 clock-names = "fclk";
449 compatible = "ti,j721e-uart", "ti,am654-uart";
452 clock-frequency = <48000000>;
453 current-speed = <115200>;
454 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
456 clock-names = "fclk";
461 compatible = "ti,j721e-uart", "ti,am654-uart";
464 clock-frequency = <48000000>;
465 current-speed = <115200>;
466 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
468 clock-names = "fclk";
473 compatible = "ti,j721e-uart", "ti,am654-uart";
476 clock-frequency = <48000000>;
477 current-speed = <115200>;
478 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
480 clock-names = "fclk";
485 compatible = "ti,j721e-uart", "ti,am654-uart";
488 clock-frequency = <48000000>;
489 current-speed = <115200>;
490 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
492 clock-names = "fclk";
497 compatible = "ti,j721e-uart", "ti,am654-uart";
500 clock-frequency = <48000000>;
501 current-speed = <115200>;
502 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
504 clock-names = "fclk";
509 compatible = "ti,j721e-uart", "ti,am654-uart";
512 clock-frequency = <48000000>;
513 current-speed = <115200>;
514 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
516 clock-names = "fclk";
521 compatible = "ti,j721e-uart", "ti,am654-uart";
524 clock-frequency = <48000000>;
525 current-speed = <115200>;
526 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
528 clock-names = "fclk";
533 compatible = "ti,j721e-uart", "ti,am654-uart";
536 clock-frequency = <48000000>;
537 current-speed = <115200>;
538 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
540 clock-names = "fclk";
545 compatible = "ti,j721e-uart", "ti,am654-uart";
548 clock-frequency = <48000000>;
549 current-speed = <115200>;
550 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
552 clock-names = "fclk";
556 main_i2c0: i2c@2000000 {
557 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
560 #address-cells = <1>;
561 #size-cells = <0>;
562 clock-names = "fck";
564 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
568 main_i2c1: i2c@2010000 {
569 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
572 #address-cells = <1>;
573 #size-cells = <0>;
574 clock-names = "fck";
576 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
580 main_i2c2: i2c@2020000 {
581 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 clock-names = "fck";
588 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
592 main_i2c3: i2c@2030000 {
593 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 clock-names = "fck";
600 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
604 main_i2c4: i2c@2040000 {
605 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 clock-names = "fck";
612 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
616 main_i2c5: i2c@2050000 {
617 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
620 #address-cells = <1>;
621 #size-cells = <0>;
622 clock-names = "fck";
624 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
628 main_i2c6: i2c@2060000 {
629 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 clock-names = "fck";
636 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
641 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
644 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
645 clock-names = "clk_ahb", "clk_xin";
647 ti,otap-del-sel-legacy = <0x0>;
648 ti,otap-del-sel-mmc-hs = <0x0>;
649 ti,otap-del-sel-ddr52 = <0x6>;
650 ti,otap-del-sel-hs200 = <0x8>;
651 ti,otap-del-sel-hs400 = <0x5>;
652 ti,itap-del-sel-legacy = <0x10>;
653 ti,itap-del-sel-mmc-hs = <0xa>;
654 ti,itap-del-sel-ddr52 = <0x3>;
655 ti,strobe-sel = <0x77>;
656 ti,clkbuf-sel = <0x7>;
657 ti,trm-icp = <0x8>;
658 bus-width = <8>;
659 mmc-ddr-1_8v;
660 mmc-hs200-1_8v;
661 mmc-hs400-1_8v;
662 dma-coherent;
667 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
670 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
671 clock-names = "clk_ahb", "clk_xin";
673 ti,otap-del-sel-legacy = <0x0>;
674 ti,otap-del-sel-sd-hs = <0x0>;
675 ti,otap-del-sel-sdr12 = <0xf>;
676 ti,otap-del-sel-sdr25 = <0xf>;
677 ti,otap-del-sel-sdr50 = <0xc>;
678 ti,otap-del-sel-sdr104 = <0x5>;
679 ti,otap-del-sel-ddr50 = <0xc>;
680 ti,itap-del-sel-legacy = <0x0>;
681 ti,itap-del-sel-sd-hs = <0x0>;
682 ti,itap-del-sel-sdr12 = <0x0>;
683 ti,itap-del-sel-sdr25 = <0x0>;
684 ti,clkbuf-sel = <0x7>;
685 ti,trm-icp = <0x8>;
686 dma-coherent;
691 compatible = "ti,j721e-wiz-10g";
692 #address-cells = <1>;
693 #size-cells = <1>;
694 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
696 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
697 num-lanes = <4>;
698 #reset-cells = <1>;
701 assigned-clocks = <&k3_clks 292 85>;
702 assigned-clock-parents = <&k3_clks 292 89>;
704 wiz0_pll0_refclk: pll0-refclk {
706 clock-output-names = "wiz0_pll0_refclk";
707 #clock-cells = <0>;
708 assigned-clocks = <&wiz0_pll0_refclk>;
709 assigned-clock-parents = <&k3_clks 292 85>;
712 wiz0_pll1_refclk: pll1-refclk {
714 clock-output-names = "wiz0_pll1_refclk";
715 #clock-cells = <0>;
716 assigned-clocks = <&wiz0_pll1_refclk>;
717 assigned-clock-parents = <&k3_clks 292 85>;
720 wiz0_refclk_dig: refclk-dig {
722 clock-output-names = "wiz0_refclk_dig";
723 #clock-cells = <0>;
724 assigned-clocks = <&wiz0_refclk_dig>;
725 assigned-clock-parents = <&k3_clks 292 85>;
728 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
730 #clock-cells = <0>;
734 compatible = "ti,j721e-serdes-10g";
736 reg-names = "torrent_phy";
738 reset-names = "torrent_reset";
740 clock-names = "refclk";
741 #address-cells = <1>;
742 #size-cells = <0>;
747 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
752 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
753 interrupt-names = "link_state";
756 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
757 max-link-speed = <3>;
758 num-lanes = <4>;
759 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
761 clock-names = "fck";
762 #address-cells = <3>;
763 #size-cells = <2>;
764 bus-range = <0x0 0xff>;
765 cdns,no-bar-match-nbits = <64>;
766 vendor-id = <0x104c>;
767 device-id = <0xb00f>;
768 msi-map = <0x0 &gic_its 0x0 0x10000>;
769 dma-coherent;
772 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
775 pcie1_ep: pcie-ep@2910000 {
776 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
781 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
782 interrupt-names = "link_state";
784 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
785 max-link-speed = <3>;
786 num-lanes = <4>;
787 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
789 clock-names = "fck";
790 max-functions = /bits/ 8 <6>;
791 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
792 dma-coherent;
795 usbss0: cdns-usb@4104000 {
796 compatible = "ti,j721e-usb";
798 dma-coherent;
799 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
801 clock-names = "ref", "lpm";
802 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
803 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
804 #address-cells = <2>;
805 #size-cells = <2>;
813 reg-names = "otg", "xhci", "dev";
817 interrupt-names = "host",
820 maximum-speed = "super-speed";
822 cdns,phyrst-a-enable;
827 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
829 gpio-controller;
830 #gpio-cells = <2>;
831 interrupt-parent = <&main_gpio_intr>;
834 interrupt-controller;
835 #interrupt-cells = <2>;
837 ti,davinci-gpio-unbanked = <0>;
838 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
840 clock-names = "gpio";
845 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
847 gpio-controller;
848 #gpio-cells = <2>;
849 interrupt-parent = <&main_gpio_intr>;
852 interrupt-controller;
853 #interrupt-cells = <2>;
855 ti,davinci-gpio-unbanked = <0>;
856 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
858 clock-names = "gpio";
863 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
865 gpio-controller;
866 #gpio-cells = <2>;
867 interrupt-parent = <&main_gpio_intr>;
870 interrupt-controller;
871 #interrupt-cells = <2>;
873 ti,davinci-gpio-unbanked = <0>;
874 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
876 clock-names = "gpio";
881 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
883 gpio-controller;
884 #gpio-cells = <2>;
885 interrupt-parent = <&main_gpio_intr>;
888 interrupt-controller;
889 #interrupt-cells = <2>;
891 ti,davinci-gpio-unbanked = <0>;
892 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
894 clock-names = "gpio";
899 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
902 #address-cells = <1>;
903 #size-cells = <0>;
904 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
910 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
913 #address-cells = <1>;
914 #size-cells = <0>;
915 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
921 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
924 #address-cells = <1>;
925 #size-cells = <0>;
926 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
932 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
935 #address-cells = <1>;
936 #size-cells = <0>;
937 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
943 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
946 #address-cells = <1>;
947 #size-cells = <0>;
948 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
954 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
957 #address-cells = <1>;
958 #size-cells = <0>;
959 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
965 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
968 #address-cells = <1>;
969 #size-cells = <0>;
970 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
976 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
979 #address-cells = <1>;
980 #size-cells = <0>;
981 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
987 compatible = "ti,j7-rti-wdt";
990 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
991 assigned-clocks = <&k3_clks 252 1>;
992 assigned-clock-parents = <&k3_clks 252 5>;
996 compatible = "ti,j7-rti-wdt";
999 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1000 assigned-clocks = <&k3_clks 253 1>;
1001 assigned-clock-parents = <&k3_clks 253 5>;
1005 compatible = "ti,am654-timer";
1009 clock-names = "fck";
1010 assigned-clocks = <&k3_clks 49 1>;
1011 assigned-clock-parents = <&k3_clks 49 2>;
1012 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1013 ti,timer-pwm;
1017 compatible = "ti,am654-timer";
1021 clock-names = "fck";
1022 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1023 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1024 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1025 ti,timer-pwm;
1029 compatible = "ti,am654-timer";
1033 clock-names = "fck";
1034 assigned-clocks = <&k3_clks 51 1>;
1035 assigned-clock-parents = <&k3_clks 51 2>;
1036 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1037 ti,timer-pwm;
1041 compatible = "ti,am654-timer";
1045 clock-names = "fck";
1046 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1047 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1048 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1049 ti,timer-pwm;
1053 compatible = "ti,am654-timer";
1057 clock-names = "fck";
1058 assigned-clocks = <&k3_clks 53 1>;
1059 assigned-clock-parents = <&k3_clks 53 2>;
1060 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1061 ti,timer-pwm;
1065 compatible = "ti,am654-timer";
1069 clock-names = "fck";
1070 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1071 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1072 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1073 ti,timer-pwm;
1077 compatible = "ti,am654-timer";
1081 clock-names = "fck";
1082 assigned-clocks = <&k3_clks 55 1>;
1083 assigned-clock-parents = <&k3_clks 55 2>;
1084 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1085 ti,timer-pwm;
1089 compatible = "ti,am654-timer";
1093 clock-names = "fck";
1094 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1095 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1096 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1097 ti,timer-pwm;
1101 compatible = "ti,am654-timer";
1105 clock-names = "fck";
1106 assigned-clocks = <&k3_clks 58 1>;
1107 assigned-clock-parents = <&k3_clks 58 2>;
1108 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1109 ti,timer-pwm;
1113 compatible = "ti,am654-timer";
1117 clock-names = "fck";
1118 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1119 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1120 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1121 ti,timer-pwm;
1125 compatible = "ti,am654-timer";
1129 clock-names = "fck";
1130 assigned-clocks = <&k3_clks 60 1>;
1131 assigned-clock-parents = <&k3_clks 60 2>;
1132 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1133 ti,timer-pwm;
1137 compatible = "ti,am654-timer";
1141 clock-names = "fck";
1142 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1143 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1144 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1145 ti,timer-pwm;
1149 compatible = "ti,am654-timer";
1153 clock-names = "fck";
1154 assigned-clocks = <&k3_clks 63 1>;
1155 assigned-clock-parents = <&k3_clks 63 2>;
1156 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1157 ti,timer-pwm;
1161 compatible = "ti,am654-timer";
1165 clock-names = "fck";
1166 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1167 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1168 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1169 ti,timer-pwm;
1173 compatible = "ti,am654-timer";
1177 clock-names = "fck";
1178 assigned-clocks = <&k3_clks 65 1>;
1179 assigned-clock-parents = <&k3_clks 65 2>;
1180 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1181 ti,timer-pwm;
1185 compatible = "ti,am654-timer";
1189 clock-names = "fck";
1190 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1191 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1192 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1193 ti,timer-pwm;
1197 compatible = "ti,am654-timer";
1201 clock-names = "fck";
1202 assigned-clocks = <&k3_clks 67 1>;
1203 assigned-clock-parents = <&k3_clks 67 2>;
1204 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1205 ti,timer-pwm;
1209 compatible = "ti,am654-timer";
1213 clock-names = "fck";
1214 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1215 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1216 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1217 ti,timer-pwm;
1221 compatible = "ti,am654-timer";
1225 clock-names = "fck";
1226 assigned-clocks = <&k3_clks 69 1>;
1227 assigned-clock-parents = <&k3_clks 69 2>;
1228 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1229 ti,timer-pwm;
1233 compatible = "ti,am654-timer";
1237 clock-names = "fck";
1238 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1239 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1240 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1241 ti,timer-pwm;
1245 compatible = "ti,j7200-r5fss";
1246 ti,cluster-mode = <1>;
1247 #address-cells = <1>;
1248 #size-cells = <1>;
1251 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1254 compatible = "ti,j7200-r5f";
1257 reg-names = "atcm", "btcm";
1259 ti,sci-dev-id = <245>;
1260 ti,sci-proc-ids = <0x06 0xff>;
1262 firmware-name = "j7200-main-r5f0_0-fw";
1263 ti,atcm-enable = <1>;
1264 ti,btcm-enable = <1>;
1269 compatible = "ti,j7200-r5f";
1272 reg-names = "atcm", "btcm";
1274 ti,sci-dev-id = <246>;
1275 ti,sci-proc-ids = <0x07 0xff>;
1277 firmware-name = "j7200-main-r5f0_1-fw";
1278 ti,atcm-enable = <1>;
1279 ti,btcm-enable = <1>;
1285 compatible = "ti,j721e-esm";
1287 ti,esm-pins = <656>, <657>;