Lines Matching +full:0 +full:x33d00000
10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
45 reg = <0x4044 0x10>;
52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
64 <0x00 0x01900000 0x00 0x100000>, /* GICR */
65 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
66 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
67 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
74 reg = <0x00 0x01820000 0x00 0x10000>;
75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
83 reg = <0x00 0x00a00000 0x00 0x800>;
97 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
104 reg = <0x00 0x310e0000 0x00 0x4000>;
111 ti,interrupt-ranges = <0 64 64>,
118 reg = <0x00 0x33d00000 0x00 0x100000>;
120 #interrupt-cells = <0>;
125 ti,interrupt-ranges = <0 0 256>;
132 reg = <0x00 0x32c00000 0x00 0x100000>,
133 <0x00 0x32400000 0x00 0x100000>,
134 <0x00 0x32800000 0x00 0x100000>;
141 reg = <0x00 0x30e00000 0x00 0x1000>;
147 reg = <0x00 0x31f80000 0x00 0x200>;
157 reg = <0x00 0x31f81000 0x00 0x200>;
167 reg = <0x00 0x31f82000 0x00 0x200>;
177 reg = <0x00 0x31f83000 0x00 0x200>;
187 reg = <0x00 0x31f84000 0x00 0x200>;
197 reg = <0x00 0x31f85000 0x00 0x200>;
207 reg = <0x00 0x31f86000 0x00 0x200>;
217 reg = <0x00 0x31f87000 0x00 0x200>;
227 reg = <0x00 0x31f88000 0x00 0x200>;
237 reg = <0x00 0x31f89000 0x00 0x200>;
247 reg = <0x00 0x31f8a000 0x00 0x200>;
257 reg = <0x00 0x31f8b000 0x00 0x200>;
267 reg = <0x00 0x3c000000 0x00 0x400000>,
268 <0x00 0x38000000 0x00 0x400000>,
269 <0x00 0x31120000 0x00 0x100>,
270 <0x00 0x33000000 0x00 0x40000>,
271 <0x00 0x31080000 0x00 0x40000>;
274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
282 reg = <0x00 0x31150000 0x00 0x100>,
283 <0x00 0x34000000 0x00 0x100000>,
284 <0x00 0x35000000 0x00 0x100000>,
285 <0x00 0x30b00000 0x00 0x4000>,
286 <0x00 0x30c00000 0x00 0x4000>,
287 <0x00 0x30d00000 0x00 0x4000>;
297 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
298 <0x0f>, /* TX_HCHAN */
299 <0x10>; /* TX_UHCHAN */
300 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
301 <0x0b>, /* RX_HCHAN */
302 <0x0c>; /* RX_UHCHAN */
303 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
308 reg = <0x00 0x310d0000 0x00 0x400>;
323 reg = <0x00 0xc000000 0x00 0x200000>;
325 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
330 dmas = <&main_udmap 0xca00>,
331 <&main_udmap 0xca01>,
332 <&main_udmap 0xca02>,
333 <&main_udmap 0xca03>,
334 <&main_udmap 0xca04>,
335 <&main_udmap 0xca05>,
336 <&main_udmap 0xca06>,
337 <&main_udmap 0xca07>,
338 <&main_udmap 0x4a00>;
347 #size-cells = <0>;
379 reg = <0x00 0xf00 0x00 0x100>;
381 #size-cells = <0>;
390 reg = <0x00 0x3d000 0x00 0x400>;
403 reg = <0x0 0x104200 0x0 0x50>;
406 pinctrl-single,function-mask = <0x000001ff>;
412 reg = <0x0 0x104280 0x0 0x20>;
415 pinctrl-single,function-mask = <0x0000001f>;
420 /* Proxy 0 addressing */
421 reg = <0x00 0x11c000 0x00 0x10c>;
424 pinctrl-single,function-mask = <0xffffffff>;
429 /* Proxy 0 addressing */
430 reg = <0x00 0x11c11c 0x00 0xc>;
433 pinctrl-single,function-mask = <0xffffffff>;
438 reg = <0x00 0x02800000 0x00 0x100>;
450 reg = <0x00 0x02810000 0x00 0x100>;
462 reg = <0x00 0x02820000 0x00 0x100>;
474 reg = <0x00 0x02830000 0x00 0x100>;
486 reg = <0x00 0x02840000 0x00 0x100>;
498 reg = <0x00 0x02850000 0x00 0x100>;
510 reg = <0x00 0x02860000 0x00 0x100>;
522 reg = <0x00 0x02870000 0x00 0x100>;
534 reg = <0x00 0x02880000 0x00 0x100>;
546 reg = <0x00 0x02890000 0x00 0x100>;
558 reg = <0x00 0x2000000 0x00 0x100>;
561 #size-cells = <0>;
570 reg = <0x00 0x2010000 0x00 0x100>;
573 #size-cells = <0>;
582 reg = <0x00 0x2020000 0x00 0x100>;
585 #size-cells = <0>;
594 reg = <0x00 0x2030000 0x00 0x100>;
597 #size-cells = <0>;
606 reg = <0x00 0x2040000 0x00 0x100>;
609 #size-cells = <0>;
618 reg = <0x00 0x2050000 0x00 0x100>;
621 #size-cells = <0>;
630 reg = <0x00 0x2060000 0x00 0x100>;
633 #size-cells = <0>;
642 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
646 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
647 ti,otap-del-sel-legacy = <0x0>;
648 ti,otap-del-sel-mmc-hs = <0x0>;
649 ti,otap-del-sel-ddr52 = <0x6>;
650 ti,otap-del-sel-hs200 = <0x8>;
651 ti,otap-del-sel-hs400 = <0x5>;
652 ti,itap-del-sel-legacy = <0x10>;
653 ti,itap-del-sel-mmc-hs = <0xa>;
654 ti,itap-del-sel-ddr52 = <0x3>;
655 ti,strobe-sel = <0x77>;
656 ti,clkbuf-sel = <0x7>;
657 ti,trm-icp = <0x8>;
668 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
673 ti,otap-del-sel-legacy = <0x0>;
674 ti,otap-del-sel-sd-hs = <0x0>;
675 ti,otap-del-sel-sdr12 = <0xf>;
676 ti,otap-del-sel-sdr25 = <0xf>;
677 ti,otap-del-sel-sdr50 = <0xc>;
678 ti,otap-del-sel-sdr104 = <0x5>;
679 ti,otap-del-sel-ddr50 = <0xc>;
680 ti,itap-del-sel-legacy = <0x0>;
681 ti,itap-del-sel-sd-hs = <0x0>;
682 ti,itap-del-sel-sdr12 = <0x0>;
683 ti,itap-del-sel-sdr25 = <0x0>;
684 ti,clkbuf-sel = <0x7>;
685 ti,trm-icp = <0x8>;
699 ranges = <0x5060000 0x0 0x5060000 0x10000>;
707 #clock-cells = <0>;
715 #clock-cells = <0>;
723 #clock-cells = <0>;
730 #clock-cells = <0>;
735 reg = <0x05060000 0x00010000>;
737 resets = <&serdes_wiz0 0>;
742 #size-cells = <0>;
748 reg = <0x00 0x02910000 0x00 0x1000>,
749 <0x00 0x02917000 0x00 0x400>,
750 <0x00 0x0d800000 0x00 0x00800000>,
751 <0x00 0x18000000 0x00 0x00001000>;
756 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
764 bus-range = <0x0 0xff>;
766 vendor-id = <0x104c>;
767 device-id = <0xb00f>;
768 msi-map = <0x0 &gic_its 0x0 0x10000>;
770 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
771 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
772 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
777 reg = <0x00 0x02910000 0x00 0x1000>,
778 <0x00 0x02917000 0x00 0x400>,
779 <0x00 0x0d800000 0x00 0x00800000>,
780 <0x00 0x18000000 0x00 0x08000000>;
784 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
791 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
797 reg = <0x00 0x4104000 0x00 0x100>;
810 reg = <0x00 0x6000000 0x00 0x10000>,
811 <0x00 0x6010000 0x00 0x10000>,
812 <0x00 0x6020000 0x00 0x10000>;
814 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
816 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
828 reg = <0x00 0x00600000 0x00 0x100>;
837 ti,davinci-gpio-unbanked = <0>;
839 clocks = <&k3_clks 105 0>;
846 reg = <0x00 0x00610000 0x00 0x100>;
855 ti,davinci-gpio-unbanked = <0>;
857 clocks = <&k3_clks 107 0>;
864 reg = <0x00 0x00620000 0x00 0x100>;
873 ti,davinci-gpio-unbanked = <0>;
875 clocks = <&k3_clks 109 0>;
882 reg = <0x00 0x00630000 0x00 0x100>;
891 ti,davinci-gpio-unbanked = <0>;
893 clocks = <&k3_clks 111 0>;
900 reg = <0x00 0x02100000 0x00 0x400>;
903 #size-cells = <0>;
911 reg = <0x00 0x02110000 0x00 0x400>;
914 #size-cells = <0>;
922 reg = <0x00 0x02120000 0x00 0x400>;
925 #size-cells = <0>;
933 reg = <0x00 0x02130000 0x00 0x400>;
936 #size-cells = <0>;
944 reg = <0x00 0x02140000 0x00 0x400>;
947 #size-cells = <0>;
955 reg = <0x00 0x02150000 0x00 0x400>;
958 #size-cells = <0>;
966 reg = <0x00 0x02160000 0x00 0x400>;
969 #size-cells = <0>;
977 reg = <0x00 0x02170000 0x00 0x400>;
980 #size-cells = <0>;
988 reg = <0x0 0x2200000 0x0 0x100>;
997 reg = <0x0 0x2210000 0x0 0x100>;
1006 reg = <0x00 0x2400000 0x00 0x400>;
1018 reg = <0x00 0x2410000 0x00 0x400>;
1022 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1030 reg = <0x00 0x2420000 0x00 0x400>;
1042 reg = <0x00 0x2430000 0x00 0x400>;
1046 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1054 reg = <0x00 0x2440000 0x00 0x400>;
1066 reg = <0x00 0x2450000 0x00 0x400>;
1070 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1078 reg = <0x00 0x2460000 0x00 0x400>;
1090 reg = <0x00 0x2470000 0x00 0x400>;
1094 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1102 reg = <0x00 0x2480000 0x00 0x400>;
1114 reg = <0x00 0x2490000 0x00 0x400>;
1118 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1126 reg = <0x00 0x24a0000 0x00 0x400>;
1138 reg = <0x00 0x24b0000 0x00 0x400>;
1142 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1150 reg = <0x00 0x24c0000 0x00 0x400>;
1162 reg = <0x00 0x24d0000 0x00 0x400>;
1166 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1174 reg = <0x00 0x24e0000 0x00 0x400>;
1186 reg = <0x00 0x24f0000 0x00 0x400>;
1190 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1198 reg = <0x00 0x2500000 0x00 0x400>;
1210 reg = <0x00 0x2510000 0x00 0x400>;
1214 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1222 reg = <0x00 0x2520000 0x00 0x400>;
1234 reg = <0x00 0x2530000 0x00 0x400>;
1238 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1249 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1250 <0x5d00000 0x00 0x5d00000 0x20000>;
1255 reg = <0x5c00000 0x00010000>,
1256 <0x5c10000 0x00010000>;
1260 ti,sci-proc-ids = <0x06 0xff>;
1270 reg = <0x5d00000 0x00008000>,
1271 <0x5d10000 0x00008000>;
1275 ti,sci-proc-ids = <0x07 0xff>;
1286 reg = <0x0 0x700000 0x0 0x1000>;